PIC16F872
TAD ..................................................................................... 90
Timer0
Timer0 ..................................................................... 135
Timer1 ..................................................................... 135
Wake-up from SLEEP via Interrupt ......................... 109
Watchdog Timer ...................................................... 134
TMR0 ................................................................................. 11
TMR0 Register ..................................................................... 9
TMR1CS bit ....................................................................... 41
TMR1H .............................................................................. 11
TMR1H Register .................................................................. 9
TMR1L ............................................................................... 11
TMR1L Register ................................................................... 9
TMR1ON bit ....................................................................... 41
TMR2 ................................................................................. 11
TMR2 Register ..................................................................... 9
TMR2ON bit ....................................................................... 45
TOUTPS0 bit ..................................................................... 45
TOUTPS1 bit ..................................................................... 45
TOUTPS2 bit ..................................................................... 45
TOUTPS3 bit ..................................................................... 45
TRISA ................................................................................ 11
TRISA Register .................................................................. 10
TRISB ................................................................................ 11
TRISB Register .................................................................. 10
TRISC ................................................................................ 11
TRISC Register .................................................................. 10
Clock Source Edge Select (T0SE Bit) ........................ 13
Clock Source Select (T0CS Bit) ................................. 13
Overflow Enable (T0IE Bit) ........................................ 14
Overflow Flag (T0IF Bit) ..................................... 14, 106
Overflow Interrupt .................................................... 106
RA4/T0CKI Pin, External Clock ................................... 6
Timer1 ................................................................................ 41
RC0/T1OSO/T1CKI Pin ............................................... 6
RC1/T1OSI Pin ............................................................ 6
Timers
Timer0
External Clock .................................................... 38
Interrupt ............................................................. 37
Prescaler ............................................................ 38
Prescaler Block Diagram ................................... 37
Section ............................................................... 37
T0CKI ................................................................. 38
Timer1
Asynchronous Counter Mode ............................ 43
Capacitor Selection ............................................ 43
Operation in Timer Mode ................................... 42
Oscillator ............................................................ 43
Prescaler ............................................................ 43
Resetting of Timer1 Registers ........................... 43
Resetting Timer1 using a CCP Trigger Output .. 43
Synchronized Counter Mode ............................. 42
T1CON ............................................................... 41
TMR1H .............................................................. 43
TMR1L ............................................................... 43
Timer2
U
UA ...................................................................................... 54
Update Address, UA .......................................................... 54
W
Wake-up from SLEEP ................................................ 95, 108
Interrupts ......................................................... 101, 102
MCLR Reset ............................................................ 102
Timing Diagram ....................................................... 109
WDT Reset .............................................................. 102
Watchdog Timer (WDT) ............................................. 95, 107
Block Diagram ......................................................... 107
Enable (WDTE Bit) .................................................. 107
Programming Considerations .................................. 107
RC Oscillator ........................................................... 107
Time-out Period ....................................................... 107
WDT Reset, Normal Operation .................. 99, 101, 102
WDT Reset, SLEEP .................................. 99, 101, 102
Waveform for General Call Address Sequence ................. 64
WCOL .................................................. 55, 69, 71, 73, 75, 76
WCOL Status Flag ............................................................. 69
Write Collision Detect bit, WCOL ....................................... 55
WWW, On-Line Support ...................................................... 3
Block Diagram ................................................... 45
Postscaler .......................................................... 45
Prescaler ............................................................ 45
T2CON ............................................................... 45
Timing Diagrams
A/D Conversion ........................................................ 142
Acknowledge Sequence Timing ................................. 75
Baud Rate Generator with Clock Arbitration .............. 68
BRG Reset Due to SDA Collision .............................. 80
Brown-out Reset ...................................................... 134
Bus Collision
Start Condition Timing ....................................... 79
Bus Collision During a Restart Condition (Case 1) .... 81
Bus Collision During a Restart Condition (Case2) ..... 81
Bus Collision During a Start Condition (SCL = 0) ...... 80
Bus Collision During a Stop Condition ....................... 82
Bus Collision for Transmit and Acknowledge ............. 78
Capture/Compare/PWM ........................................... 136
CLKOUT and I/O ...................................................... 133
2
I C Bus Data ............................................................ 140
2
I C Bus Start/Stop bits ............................................. 139
2
I C Master Mode First Start bit timing ........................ 69
2
I C Master Mode Reception timing ............................ 74
2
I C Master Mode Transmission timing ....................... 72
Master Mode Transmit Clock Arbitration .................... 77
Power-up Timer ....................................................... 134
Repeat Start Condition ............................................... 70
Reset ........................................................................ 134
SPI Master Mode ....................................................... 58
SPI Slave Mode (CKE = 1) ........................................ 59
SPI Slave Mode Timing (CKE = 0) ............................ 59
Start-up Timer .......................................................... 134
Stop Condition Receive or Transmit .......................... 76
Time-out Sequence on Power-up .................... 103, 104
1999 Microchip Technology Inc.
DS30221A-page 155
MICROCHIP [ MICROCHIP ]
