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PIC16F627-20/P 参数 Datasheet PDF下载

PIC16F627-20/P图片预览
型号: PIC16F627-20/P
PDF下载: 下载PDF文件 查看货源
内容描述: 基于闪存的8位CMOS微控制器 [FLASH-Based 8-Bit CMOS Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 160 页 / 1657 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F62X  
internal phase clock (Tosc) synchronization. Also, there  
is a delay in the actual incrementing of TMR1 after syn-  
chronization.  
7.1  
Timer1 Operation in Timer Mode  
Timer mode is selected by clearing the TMR1CS  
(T1CON<1>) bit. In this mode, the input clock to the  
timer is FOSC/4. The synchronize control bit T1SYNC  
(T1CON<2>) has no effect since the internal clock is  
always in sync.  
When the prescaler is 1:1, the external clock input is  
the same as the prescaler output. The synchronization  
of T1CKI with the internal phase clocks is accom-  
plished by sampling the prescaler output on the Q2 and  
Q4 cycles of the internal phase clocks. Therefore, it is  
necessary for T1CKI to be high for at least 2Tosc (and  
a small RC delay of 20 ns) and low for at least 2Tosc  
(and a small RC delay of 20 ns). Refer to the appropri-  
ate electrical specifications, parameters 45, 46, and 47.  
7.2  
Timer1 Operation in Synchronized  
Counter Mode  
Counter mode is selected by setting bit TMR1CS. In  
this mode the timer increments on every rising edge of  
clock input on pin RB7/T1OSI when bit T1OSCEN is  
set or pin RB6/T1OSO/T1CKI when bit T1OSCEN is  
cleared.  
When a prescaler other than 1:1 is used, the external  
clock input is divided by the asynchronous rip-  
ple-counter type prescaler so that the prescaler output  
is symmetrical. In order for the external clock to meet  
the sampling requirement, the ripple-counter must be  
taken into account. Therefore, it is necessary for T1CKI  
to have a period of at least 4Tosc (and a small RC delay  
of 40 ns) divided by the prescaler value. The only  
requirement on T1CKI high and low time is that they do  
not violate the minimum pulse width requirements of  
10 ns). Refer to the appropriate electrical specifica-  
tions, parameters 40, 42, 45, 46, and 47.  
If T1SYNC is cleared, then the external clock input is  
synchronized with internal phase clocks. The synchro-  
nization is done after the prescaler stage. The pres-  
caler stage is an asynchronous ripple-counter.  
In this configuration, during SLEEP mode, Timer1 will  
not increment even if the external clock is present,  
since the synchronization circuit is shut off. The pres-  
caler however will continue to increment.  
7.2.1  
EXTERNAL CLOCK INPUT TIMING FOR  
SYNCHRONIZED COUNTER MODE  
When an external clock input is used for Timer1 in syn-  
chronized counter mode, it must meet certain require-  
ments. The external clock requirement is due to  
FIGURE 7-1: TIMER1 BLOCK DIAGRAM  
Set flag bit  
TMR1IF on  
Overflow  
Synchronized  
0
TMR1  
clock input  
TMR1L  
TMR1H  
T1OSC  
1
TMR1ON  
on/off  
T1SYNC  
RB6/T1OSO/T1CKI  
RB7/T1OSI  
1
Synchronize  
det  
Prescaler  
1, 2, 4, 8  
T1OSCEN  
Enable  
Oscillator  
FOSC/4  
Internal  
Clock  
0
(1)  
2
SLEEP input  
T1CKPS1:T1CKPS0  
TMR1CS  
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.  
1999 Microchip Technology Inc.  
Preliminary  
DS40300B-page 51