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PIC16F627-20/P 参数 Datasheet PDF下载

PIC16F627-20/P图片预览
型号: PIC16F627-20/P
PDF下载: 下载PDF文件 查看货源
内容描述: 基于闪存的8位CMOS微控制器 [FLASH-Based 8-Bit CMOS Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 160 页 / 1657 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F62X  
When a prescaler is used, the external clock input is  
divided by the asynchronous ripple-counter type  
prescaler so that the prescaler output is symmetrical.  
For the external clock to meet the sampling  
requirement, the ripple-counter must be taken into  
account. Therefore, it is necessary for T0CKI to have a  
period of at least 4TOSC (and a small RC delay of 40 ns)  
divided by the prescaler value. The only requirement on  
T0CKI high and low time is that they do not violate the  
minimum pulse width requirement of 10 ns. Refer to  
parameters 40, 41 and 42 in the electrical specification  
of the desired device.  
6.2  
Using Timer0 with External Clock  
When an external clock input is used for Timer0, it must  
meet certain requirements. The external clock  
requirement is due to internal phase clock (TOSC)  
synchronization. Also, there is a delay in the actual  
incrementing of Timer0 after synchronization.  
6.2.1  
EXTERNAL CLOCK SYNCHRONIZATION  
When no prescaler is used, the external clock input is  
the same as the prescaler output. The synchronization  
of T0CKI with the internal phase clocks is  
accomplished by sampling the prescaler output on the  
Q2 and Q4 cycles of the internal phase clocks  
(Figure 6-5). Therefore, it is necessary for T0CKI to be  
high for at least 2TOSC (and a small RC delay of 20 ns)  
and low for at least 2TOSC (and a small RC delay of  
20 ns). Refer to the electrical specification of the  
desired device.  
6.2.2  
TIMER0 INCREMENT DELAY  
Since the prescaler output is synchronized with the  
internal clocks, there is a small delay from the time the  
external clock edge occurs to the time the TMR0 is  
actually incremented. Figure 6-5 shows the delay from  
the external clock edge to the timer incrementing.  
FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK  
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4  
Small pulse  
misses sampling  
External Clock Input or  
(2)  
Prescaler output  
(1)  
(3)  
External Clock/Prescaler  
Output after sampling  
Increment Timer0 (Q4)  
Timer0  
T0  
T0 + 1  
T0 + 2  
Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in  
measuring the interval between two edges on Timer0 input = ±4Tosc max.  
2: External clock if no prescaler selected, Prescaler output otherwise.  
3: The arrows indicate the points in time where sampling occurs.  
1999 Microchip Technology Inc.  
Preliminary  
DS40300B-page 47