PIC16F62X
4.2.2.4
PIE1 REGISTER
This register contains interrupt enable bits.
REGISTER 4-4: PIE1 REGISTER (ADDRESS 8CH)
R/W-0
EEIE
bit7
R/W-0
CMIE
R/W-0
RCIE
R/W-0
TXIE
U
R/W-0
R/W-0
R/W-0
-
CCP1IE TMR2IE TMR1IE
R = Readable bit
W = Writable bit
U = Unimplemented bit, read
as ’0’
bit0
-n = Value at POR reset
bit 7:
bit 6:
bit 5:
bit 4:
EEIE: EE Write Complete Interrupt Enable Bit
1= Enables the EE write complete interrupt
0= Disables the EE write complete interrupt
CMIE: Comparator Interrupt Enable bit
1= Enables the comparator interrupt
0= Disables the comparator interrupt
RCIE: USART Receive Interrupt Enable bit
1= Enables the USART receive interrupt
0= Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1= Enables the USART transmit interrupt
0= Disables the USART transmit interrupt
bit 3:
bit 2:
Unimplemented: Read as ‘0’
CCP1IE: CCP1 Interrupt Enable bit
1= Enables the CCP1 interrupt
0= Disables the CCP1 interrupt
bit 1:
bit 0:
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1= Enables the TMR2 to PR2 match interrupt
0= Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1= Enables the TMR1 overflow interrupt
0= Disables the TMR1 overflow interrupt
DS40300B-page 22
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
