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PIC16CE625-04/P 参数 Datasheet PDF下载

PIC16CE625-04/P图片预览
型号: PIC16CE625-04/P
PDF下载: 下载PDF文件 查看货源
内容描述: OTP 8位CMOS微控制器与EEPROM数据存储器 [OTP 8-Bit CMOS MCU with EEPROM Data Memory]
分类和应用: 存储微控制器和处理器外围集成电路光电二极管可编程只读存储器电动程控只读存储器电可擦编程只读存储器时钟
文件页数/大小: 108 页 / 2330 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16CE62X  
13.5  
EEPROM Timing  
TABLE 13-8: AC CHARACTERISTICS  
STANDARD  
MODE  
Vcc = 4.5 - 5.5V  
FAST MODE  
Parameter  
Symbol  
Units  
Remarks  
Min.  
Max.  
Min.  
Max.  
Clock frequency  
FCLK  
THIGH  
TLOW  
TR  
4000  
4700  
100  
600  
1300  
400  
kHz  
ns  
Clock high time  
Clock low time  
ns  
SDA and SCL rise time  
SDA and SCL fall time  
START condition hold time  
1000  
300  
300  
300  
ns  
(Note 1)  
(Note 1)  
TF  
ns  
THD:STA  
4000  
600  
ns  
After this period the first  
clock pulse is generated  
START condition setup time  
TSU:STA  
4700  
600  
ns  
Only relevant for repeated  
START condition  
Data input hold time  
Data input setup time  
STOP condition setup time  
Output valid from clock  
Bus free time  
THD:DAT  
TSU:DAT  
TSU:STO  
TAA  
0
0
ns  
ns  
ns  
ns  
ns  
(Note 2)  
250  
4000  
100  
600  
3500  
900  
(Note 2)  
TBUF  
4700  
1300  
Time the bus must be free  
before a new transmission  
can start  
Output fall time from VIH  
minimum to VIL maximum  
TOF  
TSP  
250  
50  
20 +0.1  
CB  
250  
50  
ns  
ns  
(Note 1), CB 100 pF  
Input filter spike suppression  
(SDA and SCL pins)  
(Note 3)  
Write cycle time  
Endurance  
TWR  
10  
10  
ms  
Byte or Page mode  
10M  
1M  
10M  
1M  
25°C, Vcc = 5.0V, Block  
Mode (Note 4)  
cycles  
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.  
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region  
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.  
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved  
noise spike suppression. This eliminates the need for a TI specification for standard operation.  
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-  
cation, please consult the Total Endurance Model which can be obtained on our website.  
FIGURE 13-7: BUS TIMING DATA  
TR  
TF  
THIGH  
TLOW  
SCL  
TSU:STA  
THD:DAT  
TSU:DAT  
TSU:STO  
THD:STA  
SDA  
IN  
TSP  
TAA  
THD:STA  
TAA  
TBUF  
SDA  
OUT  
DS40182A-page 92  
Preliminary  
1998 Microchip Technology Inc.  
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