PIC16CE62X
FIGURE 13-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
FIGURE 13-5: BROWN-OUT RESET TIMING
BVDD
VDD
35
TABLE 13-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Typ†
Max Units
Conditions
30
31
TmcL MCLR Pulse Width (low)
2000
7*
—
—
ns
-40° to +85°C
Twdt
Watchdog Timer Time-out Period
18
33*
ms
VDD = 5.0V, -40° to +85°C
(No Prescaler)
32
33
34
35
Tost
Oscillation Start-up Timer Period
—
1024 TOSC
—
132*
2.0
—
—
ms
µs
TOSC = OSC1 period
Tpwrt Power-up Timer Period
28*
72
—
—
VDD = 5.0V, -40° to +85°C
TIOZ
I/O hi-impedance from MCLR low
Brown-out Reset Pulse Width
TBOR
100*
µs 3.7V ≤ VDD ≤ 4.3V
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS40182A-page 90
Preliminary
1998 Microchip Technology Inc.