PIC16F7X
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
SPECIAL FUNCTION REGISTER SUMMARY
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(2)
Bank 0
(4)
INDF
TMR0
PCL
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
00h
01h
Timer0 Module’s Register
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
0001 1xxx 000q quuu
(4)
Program Counter's (PC) Least Significant Byte
02h
(4)
STATUS
FSR
IRP
Indirect data memory address pointer
PORTA Data Latch when written: PORTA pins when read
RP1
RP0
TO
PD
Z
DC
C
03h
(4)
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
04h
05h
06h
07h
PORTA
PORTB
PORTC
PORTD
—
—
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
(5)
08h
(5)
PORTE
PCLATH
INTCON
PIR1
—
—
—
—
—
—
—
—
RE2
RE1
RE0
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
09h
(1,4)
Write Buffer for the upper 5 bits of the Program Counter
0Ah
(4)
GIE
PEIE
ADIF
—
T0IE
RCIF
—
INTE
TXIF
—
RBIE
SSPIF
—
T0IF
CCP1IF
—
INTF
TMR2IF
—
RBIF
0Bh
(3)
0Ch
TMR1IF 0000 0000 0000 0000
PSPIF
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
PIR2
—
CCP2IF ---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
TMR1L
Holding register for the Least Significant Byte of the 16-bit TMR1 Register
Holding register for the Most Significant Byte of the 16-bit TMR1 Register
TMR1H
T1CON
TMR2
xxxx xxxx uuuu uuuu
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
Timer2 Module’s Register
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
—
Synchronous Serial Port Receive Buffer/Transmit Register
WCOL SSPOV SSPEN CKP SSPM3
xxxx xxxx uuuu uuuu
SSPM0 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
SSPM2
SSPM1
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
—
—
CCP1X
SREN
CCP1Y
CREN
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
SPEN
RX9
—
FERR
OERR
RX9D
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
—
—
CCP2X
CCP2Y
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
A/D Result Register Byte
xxxx xxxx uuuu uuuu
GO/
DONE
1Fh
ADCON0
ADCS1 ADCS0
CHS2
CHS1
CHS0
—
ADON
0000 00-0 0000 00-0
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) RESETS include external RESET through MCLR and Watchdog Timer Reset.
3: Bits PSPIE and PSPIF are reserved on the 28-pin devices; always maintain these bits clear.
4: These registers can be addressed from any bank.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
2000 Microchip Technology Inc.
Advance Information
DS30325A-page 15
MICROCHIP [ MICROCHIP ]
