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PIC16F873A-I/SP 参数 Datasheet PDF下载

PIC16F873A-I/SP图片预览
型号: PIC16F873A-I/SP
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚增强型闪存微控制器 [28/40-pin Enhanced FLASH Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 222 页 / 3815 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F87XA  
FIGURE 4-7:  
PORTC BLOCK DIAGRAM  
(PERIPHERAL OUTPUT  
OVERRIDE) RC<4:3>  
4.3  
PORTC and the TRISC Register  
PORTC is an 8-bit wide, bi-directional port. The corre-  
sponding data direction register is TRISC. Setting a  
TRISC bit (= 1) will make the corresponding PORTC  
pin an input (i.e., put the corresponding output driver in  
a Hi-Impedance mode). Clearing a TRISC bit (= 0) will  
make the corresponding PORTC pin an output (i.e., put  
the contents of the output latch on the selected pin).  
Port/Peripheral Select(2)  
Peripheral Data Out  
Data Bus  
0
VDD  
D
Q
P
I/O  
WR  
Port  
pin(1)  
1
PORTC is multiplexed with several peripheral functions  
(Table 4-5). PORTC pins have Schmitt Trigger input  
buffers.  
When the I2C module is enabled, the PORTC<4:3>  
pins can be configured with normal I2C levels, or with  
SMBus levels, by using the CKE bit (SSPSTAT<6>).  
Q
CK  
Data Latch  
D
Q
Q
WR  
TRIS  
CK  
N
TRIS Latch  
Vss  
When enabling peripheral functions, care should be  
taken in defining TRIS bits for each PORTC pin. Some  
peripherals override the TRIS bit to make a pin an out-  
put, while other peripherals override the TRIS bit to  
make a pin an input. Since the TRIS bit override is in  
effect while the peripheral is enabled, read-modify-  
write instructions (BSF, BCF, XORWF) with TRISC as  
the destination, should be avoided. The user should  
refer to the corresponding peripheral section for the  
correct TRIS bit settings.  
RD  
TRIS  
Schmitt  
Trigger  
Peripheral  
OE(3)  
Q
D
Schmitt  
Trigger  
EN  
with  
RD  
Port  
SMBus  
Levels  
0
SSPl Input  
1
CKE  
SSPSTAT<6>  
FIGURE 4-6:  
PORTC BLOCK DIAGRAM  
(PERIPHERAL OUTPUT  
OVERRIDE) RC<2:0>,  
RC<7:5>  
Note 1: I/O pins have diode protection to VDD and VSS.  
2: Port/Peripheral Select signal selects between port data  
and peripheral output.  
3: Peripheral OE (output enable) is only activated if  
Peripheral Select is active.  
Port/Peripheral Select(2)  
Peripheral Data Out  
Data Bus  
VDD  
P
0
1
D
Q
Q
I/O  
WR  
pin(1)  
Port  
CK  
Data Latch  
D
Q
Q
WR  
TRIS  
CK  
N
TRIS Latch  
VSS  
RD  
TRIS  
Schmitt  
Trigger  
Peripheral  
OE(3)  
Q
D
EN  
RD  
Port  
Peripheral Input  
Note 1: I/O pins have diode protection to VDD and VSS.  
2: Port/Peripheral Select signal selects between port  
data and peripheral output.  
3: Peripheral OE (output enable) is only activated if  
Peripheral Select is active.  
DS39582A-page 44  
AdvanceInformation  
2001 Microchip Technology Inc.