PIC16F87XA
FIGURE 17-10:
PARALLEL SLAVE PORT TIMING (PIC16F874A/877A ONLY)
RE2/CS
RE0/RD
RE1/WR
65
RD7:RD0
62
64
63
Note: Refer to Figure 17-3 for load conditions.
TABLE 17-8: PARALLEL SLAVE PORT REQUIREMENTS (PIC16F874A/877A ONLY)
Parameter
Symbol
Characteristic
Min Typ† Max Units Conditions
No.
62
TdtV2wrH Data in valid before WR↑ or CS↑ (setup time)
20
20
35
—
10
—
—
—
—
—
—
—
—
80
30
ns
ns
ns
ns
ns
63*
TwrH2dtI
WR↑ or CS↑ to data–in invalid (hold time) Standard(F)
Extended(LF)
64
65
TrdL2dtV
TrdH2dtI
RD↓ and CS↓ to data–out valid
RD↑ or CS↓ to data–out invalid
*
These parameters are characterized but not tested.
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 185
MICROCHIP [ MICROCHIP ]
