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PIC16F873A-I/SO 参数 Datasheet PDF下载

PIC16F873A-I/SO图片预览
型号: PIC16F873A-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚增强型闪存微控制器 [28/40-pin Enhanced FLASH Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 222 页 / 3815 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F87XA  
2
9.4.1  
REGISTERS  
9.4  
I C Mode  
The MSSP module has six registers for I2C operation.  
These are:  
The MSSP module in I2C mode fully implements all  
master and slave functions (including general call sup-  
port) and provides interrupts on START and STOP bits  
in hardware to determine a free bus (multi-master func-  
tion). The MSSP module implements the standard  
mode specifications, as well as 7-bit and 10-bit  
addressing.  
• MSSP Control Register (SSPCON)  
• MSSP Control Register 2 (SSPCON2)  
• MSSP Status Register (SSPSTAT)  
• Serial Receive/Transmit Buffer (SSPBUF)  
• MSSP Shift Register (SSPSR) - Not directly  
accessible  
Two pins are used for data transfer:  
• Serial clock (SCL) - RC3/SCK/SCL  
• Serial data (SDA) - RC4/SDI/SDA  
• MSSP Address Register (SSPADD)  
SSPCON, SSPCON2 and SSPSTAT are the control  
and status registers in I2C mode operation. The  
SSPCON and SSPCON2 registers are readable and  
writable. The lower 6 bits of the SSPSTAT are read  
only. The upper two bits of the SSPSTAT are read/  
write.  
The user must configure these pins as inputs or outputs  
through the TRISC<4:3> bits.  
FIGURE 9-7:  
MSSP BLOCK DIAGRAM  
(I2C MODE)  
SSPSR is the shift register used for shifting data in or  
out. SSPBUF is the buffer register to which data bytes  
are written to or read from.  
Internal  
Data Bus  
Read  
Write  
SSPADD register holds the slave device address  
when the SSP is configured in I2C Slave mode. When  
the SSP is configured in Master mode, the lower  
seven bits of SSPADD act as the baud rate generator  
reload value.  
SSPBUF reg  
RC3/SCK/SCL  
Shift  
Clock  
In receive operations, SSPSR and SSPBUF together  
create a double buffered receiver. When SSPSR  
receives a complete byte, it is transferred to SSPBUF  
and the SSPIF interrupt is set.  
SSPSR reg  
RC4/  
SDI/  
SDA  
MSb  
LSb  
Addr Match  
Match Detect  
During transmission, the SSPBUF is not double buff-  
ered. A write to SSPBUF will write to both SSPBUF and  
SSPSR.  
SSPADD reg  
START and  
Set, Reset  
S, P bits  
(SSPSTAT reg)  
STOP bit Detect  
DS39582A-page 78  
AdvanceInformation  
2001 Microchip Technology Inc.  
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