PIC16F87XA
8.2.2
TIMER1 MODE SELECTION
8.2
Compare Mode
Timer1 must be running in Timer mode, or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven high
• Driven low
8.2.3
SOFTWARE INTERRUPT MODE
• Remains unchanged
When Generate Software Interrupt mode is chosen, the
CCP1 pin is not affected. The CCPIF bit is set, causing
a CCP interrupt (if enabled).
The action on the pin is based on the value of control
bits, CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit, CCP1IF is set.
8.2.4
SPECIAL EVENT TRIGGER
FIGURE 8-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>).
Special Event Trigger
The special event trigger output of CCP2 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled).
Set Flag bit CCP1IF
(PIR1<2>)
RC2/CCP1
pin
CCPR1H CCPR1L
Note: The special event trigger from the
CCP1and CCP2 modules will not set inter-
rupt flag bit TMR1IF (PIR1<0>).
Q
S
R
Output
Logic
Comparator
Match
TRISC<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
8.2.1
CCP PIN CONFIGURATION
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the PORTC I/O
data latch.
DS39582A-page 64
AdvanceInformation
2001 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
