PIC16F87XA
11.5 A/D Operation During SLEEP
Note: For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To allow the con-
version to occur during SLEEP, ensure the
SLEEPinstruction immediately follows the
instruction that sets the GO/DONE bit.
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conver-
sion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D mod-
ule will then be turned off, although the ADON bit will
remain set.
11.6 Effects of a RESET
A device RESET forces all registers to their RESET
state. This forces the A/D module to be turned off, and
any conversion is aborted. All A/D input pins are con-
figured as analog inputs.
The value that is in the ADRESH:ADRESL registers is
not modified for
a
Power-on Reset. The
When the A/D clock source is another clock option (not
RC), a SLEEPinstruction will cause the present conver-
sion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
Turning off the A/D places the A/D module in its lowest
current consumption state.
TABLE 11-2: REGISTERS/BITS ASSOCIATED WITH A/D
Value on
POR,
BOR
Value on
MCLR,
WDT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh,
INTCON
GIE
PEIE TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
10Bh,18Bh
(1)
0Ch
8Ch
1Eh
9Eh
1Fh
9Fh
85h
05h
PIR1
PIE1
PSPIF
PSPIE
ADIF
ADIE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
xxxx xxxx uuuu uuuu
(1)
ADRESH A/D Result Register High Byte
ADRESL A/D Result Register Low Byte
ADCON0 ADCS1 ADCS0 CHS2
xxxx xxxx uuuu uuuu
CHS1
—
CHS0 GO/DONE
—
ADON 0000 00-0 0000 00-0
ADCON1
TRISA
ADFM ADCS2
—
PCFG3
PCFG2 PCFG1 PCFG0 00-- 0000 00-- 0000
—
—
—
—
PORTA Data Direction Register
PORTA Data Latch when written: PORTA pins when read
--11 1111 --11 1111
PORTA
TRISE
--0x 0000 --0u 0000
0000 -111 0000 -111
---- -xxx ---- -uuu
(1)
89h
IBF
—
OBF
—
IBOV PSPMODE
—
—
PORTE Data Direction bits
RE2 RE1 RE0
(1)
09h
PORTE
—
—
Legend: x= unknown, u= unchanged, -= unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note 1: These registers are not available on 28-pin devices.
2001 Microchip Technology Inc.
Advance Information
DS39582A-page 131
MICROCHIP [ MICROCHIP ]
