PIC16F87XA
FIGURE 10-5:
ASYNCHRONOUS RECEPTION
START
bit
START
bit
START
bit7/8 STOP bit
bit
RX (pin)
bit0
bit1
STOP
bit
STOP
bit
bit0
bit7/8
bit7/8
Rcv Shift
Reg
Rcv Buffer Reg
Word 2
RCREG
Word 1
RCREG
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
When setting up an Asynchronous Reception, follow
these steps:
6. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE is set.
1. Initialize the SPBRG register for the appropriate
baud rate. If a high speed baud rate is desired,
set bit BRGH (Section 10.1).
7. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
2. Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
8. Read the 8-bit received data by reading the
RCREG register.
3. If interrupts are desired, then set enable bit
RCIE.
9. If any error occurred, clear the error by clearing
enable bit CREN.
4. If 9-bit reception is desired, then set bit RX9.
5. Enable the reception by setting bit CREN.
10. If using interrupts, ensure that GIE and PEIE
(bits 7 and 6) of the INTCON register are set.
TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Value on:
POR,
BOR
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh, 8Bh, INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE INTE
RBIE TMR0IF
INTF
R0IF
0000 000x 0000 000u
(1)
0Ch
18h
1Ah
8Ch
98h
99h
PIR1
PSPIF
SPEN
ADIF
RX9
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
FERR OERR RX9D
0000 0000 0000 0000
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
RCSTA
SREN CREN
—
RCREG USART Receive Register
(1)
PIE1
PSPIE
CSRC
ADIE
TX9
RCIE
TXIE SSPIE CCP1IE TMR2IE TMR1IE
SYNC BRGH TRMT TX9D
TXSTA
TXEN
—
SPBRG Baud Rate Generator Register
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous reception.
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.
DS39582A-page 116
AdvanceInformation
2001 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
