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PIC16F873A-I/SO 参数 Datasheet PDF下载

PIC16F873A-I/SO图片预览
型号: PIC16F873A-I/SO
PDF下载: 下载PDF文件 查看货源
内容描述: 40分之28引脚增强型闪存微控制器 [28/40-pin Enhanced FLASH Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 222 页 / 3815 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F87XA  
When setting up an Asynchronous Transmission,  
follow these steps:  
5. Enable the transmission by setting bit TXEN,  
which will also set bit TXIF.  
6. If 9-bit transmission is selected, the ninth bit  
should be loaded in bit TX9D.  
1. Initialize the SPBRG register for the appropriate  
baud rate. If a high speed baud rate is desired,  
set bit BRGH (Section 10.1).  
7. Load data to the TXREG register (starts trans-  
mission).  
2. Enable the asynchronous serial port by clearing  
bit SYNC and setting bit SPEN.  
8. If using interrupts, ensure that GIE and PEIE  
(bits 7 and 6) of the INTCON register are set.  
3. If interrupts are desired, then set enable bit  
TXIE.  
4. If 9-bit transmission is desired, then set transmit  
bit TX9.  
FIGURE 10-2:  
ASYNCHRONOUS MASTER TRANSMISSION  
Write to TXREG  
Word 1  
BRG Output  
(Shift Clock)  
RC6/TX/CK (pin)  
START Bit  
Bit 0  
Bit 1  
Word 1  
Bit 7/8  
STOP Bit  
TXIF bit  
(Transmit Buffer  
Reg. Empty Flag)  
Word 1  
Transmit Shift Reg  
TRMT bit  
(Transmit Shift  
Reg. Empty Flag)  
FIGURE 10-3:  
ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)  
Write to TXREG  
Word 2  
Word 1  
BRG Output  
(Shift Clock)  
RC6/TX/CK (pin)  
START Bit  
START Bit  
Word 2  
Bit 0  
Bit 1  
Word 1  
Bit 7/8  
Bit 0  
STOP Bit  
TXIF bit  
(Interrupt Reg. Flag)  
TRMT bit  
(Transmit Shift  
Reg. Empty Flag)  
Word 1  
Transmit Shift Reg.  
Word 2  
Transmit Shift Reg.  
Note:  
This timing diagram shows two consecutive transmissions.  
TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION  
Value on:  
POR,  
BOR  
Value on  
all other  
RESETS  
Address  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
0Bh, 8Bh, INTCON  
10Bh,18Bh  
GIE  
PEIE TMR0IE INTE  
RBIE TMR0IF  
INTF  
R0IF  
0000 000x 0000 000u  
(1)  
0Ch  
18h  
19h  
8Ch  
98h  
99h  
PIR1  
PSPIF  
SPEN  
ADIF  
RX9  
RCIF  
TXIF  
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000  
RCSTA  
SREN CREN  
FERR  
OERR  
RX9D  
0000 -00x 0000 -00x  
0000 0000 0000 0000  
TXREG USART Transmit Register  
(1)  
PIE1  
PSPIE  
CSRC  
ADIE  
TX9  
RCIE  
TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000  
TXSTA  
TXEN  
SYNC  
BRGH  
TRMT  
TX9D  
0000 -010 0000 -010  
0000 0000 0000 0000  
SPBRG Baud Rate Generator Register  
Legend: x= unknown, -= unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.  
Note 1: Bits PSPIE and PSPIF are reserved on 28-pin devices; always maintain these bits clear.  
DS39582A-page 114  
AdvanceInformation  
2001 Microchip Technology Inc.  
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