PIC16F84A
2.2
Data Memory Organization
2.2.1
GENERAL PURPOSE REGISTER FILE
The data memory is partitioned into two areas. The first
is the Special Function Registers (SFR) area, while the
second is the General Purpose Registers (GPR) area.
The SFRs control the operation of the device.
Portions of data memory are banked. This is for both
the SFR area and the GPR area. The GPR area is
banked to allow greater than 116 bytes of general
purpose RAM. The banked areas of the SFR are for the
registers that control the peripheral functions. Banking
requires the use of control bits for bank selection.
These control bits are located in the STATUS Register.
Instructions
MOVWF
and
MOVF
can move values from
the W register to any location in the register file (“F”),
and vice-versa.
The entire data memory can be accessed either
directly using the absolute address of each register file
or indirectly through the File Select Register (FSR)
value of the RP0 bit for access into the banked areas of
data memory.
Data memory is partitioned into two banks which
contain the general purpose registers and the special
function registers. Bank 0 is selected by clearing the
RP0 bit (STATUS<5>). Setting the RP0 bit selects Bank
1. Each Bank extends up to 7Fh (128 bytes). The first
twelve locations of each Bank are reserved for the
Special Function Registers. The remainder are Gen-
eral Purpose Registers implemented as static RAM.
Each General Purpose Register (GPR) is 8 bits wide
and is accessed either directly or indirectly through the
FSR (Section 2.4).
The GPR addresses in bank 1 are mapped to
addresses in bank 0. As an example, addressing loca-
tion 0Ch or 8Ch will access the same GPR.
FIGURE 2-1:
File Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
REGISTER FILE MAP -
PIC16F84A
File Address
addr.
(1)
Indirect
addr.
(1)
80h
81h
82h
83h
84h
85h
86h
87h
EEDATA
EEADR
PCLATH
INTCON
EECON1
EECON2
(1)
PCLATH
INTCON
88h
89h
8Ah
8Bh
8Ch
Indirect
TMR0
PCL
STATUS
FSR
PORTA
PORTB
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
68
General
Purpose
Registers
(SRAM)
Mapped
(accesses)
in Bank 0
4Fh
50h
CFh
D0h
7Fh
Bank 0
Bank 1
FFh
Unimplemented data memory location; read as '0'.
Note 1: Not a physical register.
DS35007A-page 6
Preliminary
©
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
