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PIC16LF1947-E/MR 参数 Datasheet PDF下载

PIC16LF1947-E/MR图片预览
型号: PIC16LF1947-E/MR
PDF下载: 下载PDF文件 查看货源
内容描述: [64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology]
分类和应用: 微控制器
文件页数/大小: 440 页 / 4740 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC16F/LF1946/47  
23.5.4 SLAVE MODE 10-BIT ADDRESS  
RECEPTION  
23.5.5 10-BIT ADDRESSING WITH ADDRESS OR  
DATA HOLD  
This section describes a standard sequence of events  
for the MSSPx module configured as an I2C Slave in  
10-bit Addressing mode.  
Reception using 10-bit addressing with AHEN or  
DHEN set is the same as with 7-bit modes. The only  
difference is the need to update the SSPxADD register  
using the UA bit. All functionality, specifically when the  
CKP bit is cleared and SCLx line is held low are the  
same. Figure 23-20 can be used as a reference of a  
slave in 10-bit addressing with AHEN set.  
Figure 23-19 is used as a visual reference for this  
description.  
This is a step by step process of what must be done by  
slave software to accomplish I2C communication.  
Figure 23-21 shows a standard waveform for a slave  
transmitter in 10-bit Addressing mode.  
1. Bus starts Idle.  
2. Master sends Start condition; S bit of SSPxSTAT  
is set; SSPxIF is set if interrupt on Start detect is  
enabled.  
3. Master sends matching high address with R/W  
bit clear; UA bit of the SSPxSTAT register is set.  
4. Slave sends ACK and SSPxIF is set.  
5. Software clears the SSPxIF bit.  
6. Software reads received address from  
SSPxBUF clearing the BF flag.  
7. Slave loads low address into SSPxADD,  
releasing SCLx.  
8. Master sends matching low address byte to the  
Slave; UA bit is set.  
Note: Updates to the SSPxADD register are not  
allowed until after the ACK sequence.  
9. Slave sends ACK and SSPxIF is set.  
Note: If the low address does not match, SSPxIF  
and UA are still set so that the slave software  
can set SSPxADD back to the high address.  
BF is not set because there is no match.  
CKP is unaffected.  
10. Slave clears SSPxIF.  
11. Slave reads the received matching address  
from SSPxBUF clearing BF.  
12. Slave loads high address into SSPxADD.  
13. Master clocks a data byte to the slave and  
clocks out the slaves ACK on the 9th SCLx  
pulse; SSPxIF is set.  
14. If SEN bit of SSPxCON2 is set, CKP is cleared  
by hardware and the clock is stretched.  
15. Slave clears SSPxIF.  
16. Slave reads the received byte from SSPxBUF  
clearing BF.  
17. If SEN is set the slave sets CKP to release the  
SCLx.  
18. Steps 13-17 repeat for each received byte.  
19. Master sends Stop to end the transmission.  
DS41414A-page 260  
Preliminary  
2010 Microchip Technology Inc.  
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