PIC16C63A/65B/73B/74B
FIGURE 5-1:
BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
5.0
I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Data
Bus
D
Q
Q
VDD
P
WR
Port
5.1
PORTA and TRISA Registers
CK
Data Latch
PORTA is a 6-bit latch.
(1)
The RA4/T0CKI pin is a Schmitt Trigger input and an
open drain output. All other RA port pins have TTL
input levels and full CMOS output drivers. All pins have
data direction bits (TRIS registers), which can config-
ure these pins as output or input.
I/O pin
N
D
Q
WR
TRIS
VSS
Analog
Q
CK
Input
TRIS Latch
Setting a TRISA register bit puts the corresponding out-
put driver in a hi-impedance mode. Clearing a bit in the
TRISA register puts the contents of the output latch on
the selected pin(s).
mode
TTL
Input
Buffer
RD TRIS
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Q
D
EN
RD Port
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin.
To A/D Converter
On the PIC16C73B/74B, PORTA pins are multiplexed
with analog inputs and analog VREF input. The opera-
tion of each pin is selected by clearing/setting the con-
trol bits in the ADCON1 register (A/D Control
Register1).
Note 1: I/O pins have protection diodes to VDD and VSS.
Note: On all RESETS, pins with analog functions
FIGURE 5-2:
BLOCK DIAGRAM OF
RA4/T0CKI PIN
are configured as analog and digital inputs.
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
Data
Bus
D
Q
Q
WR
Port
CK
I/O pin(1)
N
Data Latch
EXAMPLE 5-1:
INITIALIZING PORTA
(PIC16C73B/74B)
D
Q
VSS
WR
TRIS
BCF
CLRF
STATUS, RP0
PORTA
;
Schmitt
Trigger
Input
Q
CK
; Initialize PORTA by
; clearing output
; data latches
TRIS Latch
Buffer
BSF
STATUS, RP0 ; Select Bank 1
MOVLW
MOVWF
MOVLW
0x06
ADCON1
0xCF
; Configure all pins
; as digital inputs
; Value used to
; initialize data
; direction
RD TRIS
Q
D
EN
EN
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
RD Port
TMR0 Clock Input
Note 1: I/O pins have protection diodes to VDD and VSS.
2000 Microchip Technology Inc.
DS30605C-page 29
MICROCHIP [ MICROCHIP ]
