PIC16C63A/65B/73B/74B
11.3.2
USART SYNCHRONOUS SLAVE
RECEPTION
11.3 USART Synchronous Slave Mode
Synchronous Slave mode differs from the Master mode
in the fact that the shift clock is supplied externally at
the RC6/TX/CK pin (instead of being supplied internally
in Master mode). This allows the device to transfer or
receive data while in SLEEP mode. Slave mode is
entered by clearing bit CSRC (TXSTA<7>).
The operation of the synchronous Master and Slave
modes is identical, except in the case of the SLEEP
mode. Also, bit SREN is a “don't care” in Slave mode.
If receive is enabled by setting bit CREN prior to the
SLEEP instruction, a word may be received during
SLEEP. On completely receiving the word, the RSR
register will transfer the data to the RCREG register. If
interrupt enable bits RCIE and PEIE are set, the inter-
rupt generated will wake the chip from SLEEP. If the
global interrupt is enabled, the program will branch to
the interrupt vector (0004h), otherwise execution will
resume from the instruction following the SLEEP
instruction.
11.3.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical, except in the case of the SLEEP
mode.
If two words are written to the TXREG and then the
SLEEPinstruction is executed, the following will occur:
Steps to follow when setting up a Synchronous Slave
Reception:
a) The first word will immediately transfer to the
TSR register and transmit.
1. Enable the synchronous master serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
b) The second word will remain in TXREG register.
c) Flag bit TXIF will not be set.
d) When the first word has been shifted out of TSR,
the TXREG register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
2. If interrupts are desired, set interrupt enable bits
RCIE (PIE1<5>), PEIE (INTCON<6>), and GIE
(INTCON<7>), as required.
3. If 9-bit reception is desired, set bit RX9.
4. To enable reception, set enable bit CREN.
e) If interrupt enable bits TXIE and PEIE are set,
the interrupt will wake the chip from SLEEP. If
GIE is set, the program will branch to the inter-
rupt vector (0004h), otherwise execution will
resume from the instruction following the SLEEP
instruction.
5. Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated, if
enable bit RCIE was set.
6. Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Steps to follow when setting up a Synchronous Slave
Transmission:
7. Read the 8-bit received data by reading the
RCREG register.
1. Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
8. If any error occurred, clear the error by clearing
bit CREN.
2. Clear bits CREN and SREN.
3. If interrupts are desired, set interrupt enable bits
TXIE (PIE1<4>), PEIE (INTCON<6>), and GIE
(INTCON<7>), as required.
4. If 9-bit transmission is desired, set bit TX9.
5. Enable the transmission by setting enable bit
TXEN.
6. If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7. Start transmission by loading data to the TXREG
register.
DS30605C-page 76
2000 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
