PIC16C62B/72A
2.2
Data Memory Organization
FIGURE 2-2:
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
General
Purpose
Registers
7Fh
Bank 0
INDF
(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
—
—
REGISTER FILE MAP
File
Address
INDF
(1)
PCL
STATUS
FSR
TRISA
TRISB
TRISC
—
—
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
RP1
(1)
= 00
→
= 01
→
= 10
→
= 11
→
RP0
(STATUS<6:5>)
80h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
FFh
OPTION_REG 81h
Bank0
Bank1
Bank2 (not implemented)
Bank3 (not implemented)
Note 1:
Maintain this bit clear to ensure upward compati-
bility with future products.
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Regis-
ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some “high use” Special Function
Registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1
GENERAL PURPOSE REGISTER FILE
PCLATH
INTCON
PIR1
—
PCLATH
INTCON
PIE1
—
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
—
—
—
—
—
—
PCON
—
—
—
The register file can be accessed either directly, or indi-
rectly through the File Select Register FSR
PR2
SSPADD
SSPSTAT
—
—
—
—
—
—
—
—
—
—
ADRES
(2)
ADCON0
(2)
ADCON1
(2)
General
Purpose
Registers
—
—
—
Bank 1
Unimplemented data memory locations,
read as ’0’.
Note 1:
Not a physical register.
2:
These registers are not implemented on the
PIC16C62B, read as ’0’.
DS35008B-page 8
Preliminary
©
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
