PIC16C62B/72A
FIGURE 13-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
SS
81
SCK
(CKP = 0)
71
72
79
78
73
SCK
(CKP = 1)
80
LSb
MSb
BIT6 - - - - - -1
BIT6 - - - -1
SDO
SDI
75, 76
MSb IN
74
LSb IN
Note: Refer to Figure 13-4 for load conditions.
TABLE 13-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param. Symbol
No.
Characteristic
SCK input high time
Min
Typ† Max Units Conditions
71
TscH
Continuous
Single Byte
Continuous
Single Byte
1.25TCY + 30
—
—
—
—
—
—
—
—
—
—
ns
(slave mode)
71A
72
40
1.25TCY + 30
40
ns Note 1
TscL
SCK input low time
(slave mode)
ns
72A
73
ns Note 1
ns
TdiV2scH, Setup time of SDI data input to SCK
100
TdiV2scL
edge
73A
74
TB2B
Last clock edge of Byte1 to the 1st clock
edge of Byte2
1.5TCY + 40
—
—
—
—
ns Note 1
ns
TscH2diL, Hold time of SDI data input to SCK edge
TscL2diL
100
—
75
PIC16CXX
TdoR
SDO data output rise
time
10
20
10
10
20
10
—
—
—
25
45
25
25
45
25
50
100
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
PIC16LCXX
76
78
TdoF
TscR
SDO data output fall time
—
—
PIC16CXX
SCK output rise time
(master mode)
PIC16LCXX
79
80
TscF
SCK output fall time (master mode)
—
—
PIC16CXX
TscH2doV, SDO data output valid
TscL2doV after SCK edge
PIC16LCXX
81
TdoV2scH, SDO data output setup to SCK edge
TdoV2scL
TCY
† Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.
DS35008B-page 96
Preliminary
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
