PIC16C62B/72A
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[label] BTFSS f,b
Syntax:
[label] CLRF
0 ≤ f ≤ 127
f
Operands:
0 ≤ f ≤ 127
0 ≤ b < 7
Operands:
Operation:
00h → (f)
1 → Z
Operation:
skip if (f<b>) = 1
Status Affected: None
Status Affected:
Description:
Z
If bit ’b’ in register ’f’ is ’0’, then the next
The contents of register ’f’ are cleared
and the Z bit is set.
Description:
instruction is executed.
If bit ’b’ is ’1’, then the next instruction
is discarded and a NOPis executed
instead, making this a 2TCY instruc-
tion.
CLRW
Clear W
BTFSC
Bit Test, Skip if Clear
Syntax:
[ label ] CLRW
None
Syntax:
[label] BTFSC f,b
Operands:
Operation:
Operands:
0 ≤ f ≤ 127
0 ≤ b ≤ 7
00h → (W)
1 → Z
Operation:
skip if (f<b>) = 0
Status Affected:
Description:
Z
Status Affected: None
W register is cleared. Zero bit (Z) is
set.
If bit ’b’ in register ’f’ is ’1’, then the next
Description:
instruction is executed.
If bit ’b’ in register ’f’ is ’0’, then the next
instruction is discarded, and a NOPis
executed instead, making this a 2TCY
instruction.
CALL
Call Subroutine
CLRWDT
Syntax:
Clear Watchdog Timer
[ label ] CLRWDT
None
Syntax:
[ label ] CALL k
Operands:
Operation:
0 ≤ k ≤ 2047
Operands:
Operation:
(PC)+ 1→ TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Status Affected: None
Status Affected: TO, PD
Call Subroutine. First, return address
Description:
(PC+1) is pushed onto the stack. The
eleven bit immediate address is loaded
into PC bits <10:0>. The upper bits of
the PC are loaded from PCLATH.
CALLis a two cycle instruction.
CLRWDTinstruction resets the Watch-
Description:
dog Timer. It also resets the prescaler
of the WDT. Status bits TO and PD
are set.
DS35008B-page 70
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
