PIC16C62B/72A
7.3.1
PWM PERIOD
7.3
PWM Mode
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
Note: Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
Figure 7-3 shows a simplified block diagram of the CCP
module in PWM mode.
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 7.3.3.
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
FIGURE 7-3: SIMPLIFIED PWM BLOCK
DIAGRAM
Note: The Timer2 postscaler (see Section 6.0) is
not used in the determination of the PWM
frequency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
CCP1CON<5:4>
Duty Cycle Registers
CCPR1L
7.3.2
PWM ON-TIME
The PWM on-time is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. CCPR1L contains eight
MSbs and CCP1CON<5:4> contains two LSbs. This
CCPR1H (Slave)
Q
R
S
Comparator
10-bit
value
is
represented
by
RC2/CCP1
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
(Note 1)
TMR2
PWM on-time = (CCPR1L:CCP1CON<5:4>) •
Tosc • (TMR2 prescale value)
TRISC<2>
Comparator
PR2
Clear Timer,
CCP1 pin and
latch D.C.
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the on-time value is not latched into CCPR1H
until after a match between PR2 and TMR2 occurs (i.e.,
the period is complete). In PWM mode, CCPR1H is a
read-only register.
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM on-time. This double
buffering is essential for glitchless PWM operation.
A PWM output (Figure 7-4) has a time base (period)
and a time that the output stays high (on-time). The fre-
quency of the PWM is the inverse of the period
(1/period).
When the CCPR1H and 2-bit latch match TMR2 con-
catenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
FIGURE 7-4: PWM OUTPUT
Maximum PWM resolution (bits) for a given PWM
frequency:
Period
Fosc
Fpwm
log (
)
=
bits
Resolution
On-Time
TMR2 = PR2
log(2)
Note: If the PWM on-time value is larger than the
PWM period, the CCP1 pin will not be
cleared.
TMR2 = Duty Cycle
TMR2 = PR2
For an example PWM period and on-time calculation,
see the PICmicro™ Mid-Range Reference Manual,
(DS33023).
DS35008B-page 36
Preliminary
1999 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
