PIC16C62B/72A
7.2.1
CCP PIN CONFIGURATION
7.2
Compare Mode
The user must configure the RC2/CCP1 pin as an out-
put by clearing the TRISC<2> bit.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
Note: Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
• driven High
• driven Low
• remains Unchanged
7.2.2
TIMER1 MODE SELECTION
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). The inter-
rupt flag bit, CCP1IF, is set on all compare matches.
Timer1 must be running in Timer mode or Synchro-
nized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
FIGURE 7-2: COMPARE MODE
OPERATION BLOCK
DIAGRAM
7.2.3
SOFTWARE INTERRUPT MODE
When a generated software interrupt is chosen, the
CCP1 pin is not affected. Only a CCP interrupt is gen-
erated (if enabled).
Special event trigger will:
reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>),
and set bit GO/DONE (ADCON0<2>), which starts an A/D
conversion
7.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated,
which may be used to initiate an action.
Special Event Trigger
Set flag bit CCP1IF
(PIR1<2>)
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
CCPR1H CCPR1L
Q
S
R
Output
Logic
Comparator
match
RC2/CCP1
Pin
The special trigger output of CCP1 resets the TMR1
register pair and starts an A/D conversion (if the A/D
module is enabled).
TRISC<2>
Output Enable
TMR1H TMR1L
CCP1CON<3:0>
Mode Select
TABLE 7-3
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1
Value on
POR,
BOR
Value on
all other
resets
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0Bh,8Bh
0Ch
8Ch
87h
INTCON
GIE
—
PEIE
ADIF
ADIE
T0IE
—
INTE
—
RBIE
SSPIF
SSPIE
T0IF
INTF
RBIF
0000 000x 0000 000u
PIR1
CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
1111 1111 1111 1111
PIE1
—
—
—
TRISC
TMR1L
TMR1H
T1CON
CCPR1L
PORTC Data Direction Register
0Eh
0Fh
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1register
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
10h
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
15h
Capture/Compare/PWM register1 (LSB)
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
16h
CCPR1H Capture/Compare/PWM register1 (MSB)
CCP1CON CCP1X CCP1Y
17h
—
—
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
Legend: x= unknown, u= unchanged, -= unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.
1999 Microchip Technology Inc.
Preliminary
DS35008B-page 35
MICROCHIP [ MICROCHIP ]
