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PIC12F635-I/SN 参数 Datasheet PDF下载

PIC12F635-I/SN图片预览
型号: PIC12F635-I/SN
PDF下载: 下载PDF文件 查看货源
内容描述: 8月14日引脚,基于闪存的8位CMOS微控制器采用纳瓦技术 [8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 234 页 / 3856 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12F635/PIC16F636/639  
9.5  
Protection Against Spurious Write  
9.6  
Data EEPROM Operation During  
Code Protection  
There are conditions when the user may not want to  
write to the data EEPROM memory. To protect against  
spurious EEPROM writes, various mechanisms have  
been built in. On power-up, WREN is cleared. Also, the  
Power-up Timer (nominal 64 ms duration) prevents  
EEPROM write.  
Data memory can be code-protected by programming  
the CPD bit in the Configuration Word (Register 12-1)  
to ‘0’.  
When the data memory is code-protected, the CPU is  
able to read and write data to the data EEPROM. It is  
recommended to code-protect the program memory  
when code-protecting data memory. This prevents  
anyone from programming zeroes over the existing  
code (which will execute as NOPs) to reach an added  
routine, programmed in unused program memory,  
which outputs the contents of data memory.  
Programming unused locations in program memory to  
0’ will also help prevent data memory code protection  
from becoming breached.  
The write initiate sequence and the WREN bit together  
help prevent an accidental write during:  
• Brown-out  
• Power Glitch  
• Software Malfunction  
TABLE 9-1:  
SUMMARY OF REGISTERS ASSOCIATED WITH DATA EEPROM  
Value on  
Value on  
POR, BOR  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
all other  
Resets  
INTCON  
PIR1  
GIE  
EEIF  
EEIE  
PEIE  
LVDIF  
LVDIE  
EEDAT6  
EEADR6  
T0IE  
CRIF  
INTE  
C2IF(1)  
C2IE(1)  
EEDAT4  
EEADR4  
RAIE  
C1IF  
T0IF  
OSFIF  
INTF  
RAIF  
TMR1IF  
TMR1IE  
EEDAT0  
EEADR0  
RD  
0000 000x  
0000 00-0  
0000 00-0  
0000 0000  
0000 0000  
---- x000  
---- ----  
0000 000x  
0000 00-0  
0000 00-0  
0000 0000  
0000 0000  
---- q000  
---- ----  
PIE1  
CRIE  
C1IE  
OSFIE  
EEDAT2  
EEADR2  
WREN  
EEDAT  
EEDAT7  
EEADR7(1)  
EEDAT5  
EEADR5  
EEDAT3  
EEADR3  
WRERR  
EEDAT1  
EEADR1  
WR  
EEADR  
EECON1  
EECON2  
Legend:  
EEPROM Control Register 2 (not a physical register)  
x= unknown, u= unchanged, – = unimplemented read as ‘0’, q= value depends upon condition.  
Shaded cells are not used by the data EEPROM module.  
Note 1: PIC16F636/639 only.  
DS41232D-page 94  
© 2007 Microchip Technology Inc.  
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