PIC12F635/PIC16F636/639
9.2
Reading the EEPROM Data
Memory
9.4
Write Verify
Depending on the application, good programming
practice may dictate that the value written to the data
EEPROM should be verified (see Example 9-3) to the
desired value to be written.
To read a data memory location, the user must write the
address to the EEADR register and then set control bit
RD of the EECON1 register, as shown in Example 9-1.
The data is available, in the very next cycle, in the
EEDAT register. Therefore, it can be read in the next
instruction. EEDAT holds this value until another read, or
until it is written to by the user (during a write operation).
EXAMPLE 9-3:
WRITE VERIFY
BANKSEL EEDAT
;
MOVF
BSF
EEDAT,W
;EEDAT not changed
;from previous write
EECON1,RD ;YES, Read the
EXAMPLE 9-1:
DATA EEPROM READ
;value written
;
;Is data the same
BANKSEL EEADR
;
XORWF
BTFSS
GOTO
:
EEDAT,W
STATUS,Z
WRITE_ERR ;No, handle error
;Yes, continue
MOVLW
MOVWF
BSF
CONFIG_ADDR
EEADR
;
;Address to read
EECON1,RD
EEDAT,W
;EE Read
;Move data to W
MOVF
9.4.1
USING THE DATA EEPROM
9.3
Writing to the EEPROM Data
Memory
The data EEPROM is
a high-endurance, byte
addressable array that has been optimized for the
storage of frequently changing information (e.g.,
program variables or other data that are updated
often). When variables in one section change
frequently, while variables in another section do not
change, it is possible to exceed the total number of
write cycles to the EEPROM (specification D124)
without exceeding the total number of write cycles to a
single byte (specifications D120 and D120A). If this is
the case, then a refresh of the array must be
performed. For this reason, variables that change
infrequently (such as constants, IDs, calibration, etc.)
should be stored in Flash program memory.
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDAT register. Then the user must follow a
specific sequence to initiate the write for each byte, as
shown in Example 9-2.
The write will not initiate if the above sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment. A cycle count is executed during the
required sequence. Any number that is not equal to the
required cycles to execute the required sequence will
prevent the data from being written into the EEPROM.
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental writes
to data EEPROM due to errant (unexpected) code
execution (i.e., lost programs). The user should keep the
WREN bit clear at all times, except when updating
EEPROM. The WREN bit is not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. The EEIF bit of the
PIR1 register must be cleared by software.
EXAMPLE 9-2:
DATA EEPROM WRITE
BANKSEL EEADR
;
BSF
EECON1,WREN
;Enable write
BCF
INTCON,GIE
55h
EECON2
AAh
EECON2
;Disable INTs
;Unlock write
;
;
MOVLW
MOVWF
MOVLW
MOVWF
BSF
;
EECON1,WR
INTCON,GIE
;Start the write
;Enable INTS
BSF
© 2007 Microchip Technology Inc.
DS41232D-page 93
MICROCHIP [ MICROCHIP ]
