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PIC12F635-I/SN 参数 Datasheet PDF下载

PIC12F635-I/SN图片预览
型号: PIC12F635-I/SN
PDF下载: 下载PDF文件 查看货源
内容描述: 8月14日引脚,基于闪存的8位CMOS微控制器采用纳瓦技术 [8/14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 234 页 / 3856 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12F635/PIC16F636/639  
comparator is a digital low level. When the analog  
voltage at VIN+ is greater than the analog voltage at  
VIN-, the output of the comparator is a digital high level.  
7.0  
COMPARATOR MODULE  
Comparators are used to interface analog circuits to a  
digital circuit by comparing two analog voltages and  
providing a digital indication of their relative magnitudes.  
The comparators are very useful mixed signal building  
blocks because they provide analog functionality  
independent of the program execution. The Analog  
Comparator module includes the following features:  
The PIC12F635 contains a single comparator as  
shown in Figure 7-2.  
The PIC16F636/639 devices contains two comparators  
as shown in Figure 7-3 and Figure 7-4. The comparators  
are not independently configurable.  
• Dual comparators (PIC16F636/639 only)  
• Multiple comparator configurations  
FIGURE 7-1:  
SINGLE COMPARATOR  
• Comparator(s) output is available  
internally/externally  
VIN+  
VIN-  
+
Output  
• Programmable output polarity  
• Interrupt-on-change  
• Wake-up from Sleep  
• Timer1 gate (count enable)  
• Output synchronization to Timer1 clock input  
• Programmable voltage reference  
VIN-  
VIN+  
7.1  
Comparator Overview  
A comparator is shown in Figure 7-1 along with the  
relationship between the analog input levels and the  
digital output. When the analog voltage at VIN+ is less  
than the analog voltage at VIN-, the output of the  
Output  
Note:  
The black areas of the output of the  
comparator represents the uncertainty  
due to input offsets and response time.  
FIGURE 7-2:  
COMPARATOR OUTPUT BLOCK DIAGRAM (PIC12F635)  
CMSYNC  
To Timer1 Gate  
To COUT pin  
CINV  
0
1
D
Q
Timer1  
clock source  
(1)  
To Data Bus  
Set CMIF bit  
D
Q
Q
Q1  
EN  
RD CMCON0  
D
Q3*RD CMCON0  
EN  
CL  
Reset  
Note 1: Comparator output is latched on falling edge of Timer1 clock source.  
2: Q1 and Q3 are phases of the four-phase system clock (FOSC).  
3: Q1 is held high during Sleep mode.  
© 2007 Microchip Technology Inc.  
DS41232D-page 71  
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