PIC12F635/PIC16F636/639
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOR
Reset. After these Resets, the RAIF flag will continue
to be set if a mismatch is present.
4.2.2
INTERRUPT-ON-CHANGE
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits, IOCAx, enable
or disable the interrupt function for each pin. Refer to
Register 4-5. The interrupt-on-change is disabled on a
Power-on Reset.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt Flag
bit (RAIF) in the INTCON register.
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
interrupt by:
a) Any read or write of PORTA. This will end the
mismatch condition, then
b) Clear the flag bit RAIF.
REGISTER 4-5:
IOCA: INTERRUPT-ON-CHANGE PORTA REGISTER
U-0
—
U-0
—
R/W-0
IOCA5(2)
R/W-0
IOCA4(2)
R/W-0
IOCA3(3)
R/W-0
IOCA2
R/W-0
IOCA1
R/W-0
IOCA0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
IOCA<5:0>: Interrupt-on-Change PORTA Control bits(2,3)
1= Interrupt-on-change enabled(1)
0= Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
2: IOCA<5:4> always reads ‘0’ in XT, HS and LP Oscillator modes.
3: IOCA<3> is ignored when WUR is enabled and the device is in Sleep mode.
DS41232D-page 50
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
