PIC12F635/PIC16F636/639
TABLE 2-3:
PIC16F636/639 SPECIAL FUNCTION REGISTERS SUMMARY BANK 0
Value on
POR/BOR/
WUR
Addr Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 0
32,137
00h INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
xxxx xxxx
61,137
32,137
01h TMR0
02h PCL
Timer0 Module Register
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--xx xx00
—
Program Counter’s (PC) Least Significant Byte
26,137
32,137
03h STATUS
04h FSR
IRP
RP1
RP0
TO
PD
Z
DC
RA1
RC1
C
Indirect Data Memory Address Pointer
05h PORTA
—
—
RA5
RC5
RA4
RC4
RA3
RC3
RA2
RC2
RA0
RC0
48,137
—
06h
—
Unimplemented
07h PORTC
—
—
--xx xx00
—
57,137
—
08h
09h
—
—
Unimplemented
Unimplemented
—
—
32,137
0Ah PCLATH
0Bh INTCON
0Ch PIR1
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000
0000 000x
(2)
GIE
EEIF
PEIE
LVDIF
T0IE
CRIF
INTE
C2IF
RAIE
C1IF
T0IF
INTF
—
RAIF
28,137
30,137
—
OSFIF
TMR1IF 0000 00-0
—
0Dh
0Eh TMR1L
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1
10h T1CON
—
Unimplemented
64,137
64,137
Holding Register for the Least Significant Byte of the 16-bit TMR1
xxxx xxxx
xxxx xxxx
68,137
T1GINV TMR1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000
11h
12h
13h
14h
15h
16h
17h
—
—
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
—
—
—
—
144,137
79,137
82,137
18h WDTCON
19h CMCON0 C2OUT C1OUT
1Ah CMCON1
—
—
—
C2INV
—
WDTPS3 WDTPS2 WDTPS1 WDTPS0 SWDTEN ---0 1000
C1INV
—
CIS
—
CM2
—
CM1
CM0
0000 0000
—
—
T1GSS C2SYNC ---- --10
1Bh
—
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
—
—
1Ch
1Dh
1Eh
1Fh
Legend:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset but will set
again if the mismatch exists.
© 2007 Microchip Technology Inc.
DS41232D-page 23
MICROCHIP [ MICROCHIP ]
