PIC12F635/PIC16F636/639
TABLE 2-2:
PIC12F635 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Value on
POR/BOR/
WUR
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
Bank 1
32,137
80h INDF
Addressing this location uses contents of FSR to address data memory
(not a physical register)
xxxx xxxx
63,137
32,137
26,137
32,137
81h OPTION_REG RAPU INTEDG
T0CS
Program Counter’s (PC) Least Significant Byte
IRP RP1 RP0 TO PD
Indirect Data Memory Address Pointer
T0SE
PSA
PS2
PS1
PS0
C
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
82h PCL
83h STATUS
84h FSR
Z
DC
85h TRISIO
—
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
86h
87h
88h
89h
—
—
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
—
—
—
32,137
8Ah PCLATH
8Bh INTCON
8Ch PIE1
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000
0000 000x
(3)
GIE
EEIE
PEIE
LVDIE
T0IE
CRIE
INTE
—
RAIE
C1IE
T0IF
INTF
—
RAIF
28,137
29,137
—
OSFIE
TMR1IE 000- 00-0
8Dh
—
Unimplemented
—
8Eh PCON
—
—
—
—
IRCF2
—
ULPWUE SBOREN WUR
—
POR
LTS
BOR
SCS
--01 q-qq
-110 q000
31,137
36,137
40,137
—
8Fh OSCCON
90h OSCTUNE
IRCF1
—
IRCF0
TUN4
OSTS
TUN3
HTS
TUN2
TUN1
TUN0 ---0 0000
91h
92h
93h
—
—
—
Unimplemented
Unimplemented
Unimplemented
—
—
—
—
—
94h LVDCON
—
—
—
—
—
—
—
—
IRVST
LVDEN
—
—
LVDL2
LVDL1
LVDL0 --00 -000 --00 -000
(2)
95h WPUDA
96h IOCA
WPUDA5 WPUDA4
WPUDA2 WPUDA1 WPUDA0 --11 -111 --11 -111
IOCA5
WDA5
IOCA4
WDA4
IOCA3
—
IOCA2
WDA2
IOCA1
WDA1
IOCA0 --00 0000 --00 0000
WDA0 --11 -111 --11 -111
(2)
97h WDA
9Bh
—
Unimplemented
VREN
—
—
99h VRCON
9Ah EEDAT
9Bh EEADR
9Ch EECON1
9Dh EECON2
—
VRR
—
VR3
VR2
VR1
VR0
0-0- 0000 0-0- 0000
EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 0000 0000
EEADR7 EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 0000 0000
—
—
—
—
WRERR WREN
WR
RD
---- x000 ---- q000
---- ---- ---- ----
EEPROM Control Register 2 (not a physical register)
Unimplemented
9Eh
—
—
—
—
—
—
9Fh
Unimplemented
Legend:
– = Unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,
shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: GP3 pull-up is enabled when pin is configured as MCLR in the Configuration Word register.
3: MCLR and WDT Reset do not affect the previous value data latch. The RAIF bit will be cleared upon Reset, but will set
again if the mismatch exists.
DS41232D-page 22
© 2007 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
