PIC12F635/PIC16F636/639
2.2.2.4
PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-4.
Note:
Bit PEIE of the INTCON register must be
set to enable any peripheral interrupt.
REGISTER 2-4:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1
R/W-0
EEIE
R/W-0
LVDIE
R/W-0
CRIE
R/W-0
C2IE(1)
R/W-0
C1IE
R/W-0
OSFIE
U-0
—
R/W-0
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
EEIE: EE Write Complete Interrupt Enable bit
1= Enables the EE write complete interrupt
0= Disables the EE write complete interrupt
LVDIE: Low-Voltage Detect Interrupt Enable bit
1= Enables the LVD interrupt
0= Disables the LVD interrupt
CRIE: Cryptographic Interrupt Enable bit
1= Enables the cryptographic interrupt
0= Disables the cryptographic interrupt
C2IE: Comparator 2 Interrupt Enable bit(1)
1= Enables the Comparator 2 interrupt
0= Disables the Comparator 2 interrupt
C1IE: Comparator 1 Interrupt Enable bit
1= Enables the Comparator 1 interrupt
0= Disables the Comparator 1 interrupt
OSFIE: Oscillator Fail Interrupt Enable bit
1= Enables the oscillator fail interrupt
0= Disables the oscillator fail interrupt
bit 1
bit 0
Unimplemented: Read as ‘0’
TMR1IE: Timer1 Overflow Interrupt Enable bit
1= Enables the Timer1 overflow interrupt
0= Disables the Timer1 overflow interrupt
Note 1: PIC16F636/639 only.
© 2007 Microchip Technology Inc.
DS41232D-page 29
MICROCHIP [ MICROCHIP ]
