PIC12F635/PIC16F636/639
2.2.2.3
INTCON Register
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Interrupt Enable bit, GIE of the INTCON
register. User software should ensure the
appropriate interrupt flag bits are clear
prior to enabling an interrupt.
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for TMR0 register overflow, PORTA change and
external RA2/INT pin interrupts.
REGISTER 2-3:
INTCON: INTERRUPT CONTROL REGISTER
R/W-0
GIE
R/W-0
PEIE
R/W-0
T0IE
R/W-0
INTE
R/W-0
RAIE(1,3)
R/W-0
T0IF(2)
R/W-0
INTF
R/W-x
RAIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
GIE: Global Interrupt Enable bit
1= Enables all unmasked interrupts
0= Disables all interrupts
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PEIE: Peripheral Interrupt Enable bit
1= Enables all unmasked peripheral interrupts
0= Disables all peripheral interrupts
T0IE: Timer0 Overflow Interrupt Enable bit
1= Enables the Timer0 interrupt
0= Disables the Timer0 interrupt
INTE: RA2/INT External Interrupt Enable bit
1= Enables the RA2/INT external interrupt
0= Disables the RA2/INT external interrupt
RAIE: PORTA Change Interrupt Enable bit(1,3)
1= Enables the PORTA change interrupt
0= Disables the PORTA change interrupt
T0IF: Timer0 Overflow Interrupt Flag bit(2)
1= TMR0 register has overflowed (must be cleared in software)
0= TMR0 register did not overflow
INTF: RA2/INT External Interrupt Flag bit
1= The RA2/INT external interrupt occurred (must be cleared in software)
0= The RA2/INT external interrupt did not occur
RAIF: PORTA Change Interrupt Flag bit
1 = When at least one of the PORTA general purpose I/O pins changed state (must be cleared in
software)
0= None of the PORTA general purpose I/O pins have changed state
Note 1: IOCA register must also be enabled.
2: T0IF bit is set when Timer0 rolls over. Timer0 is unchanged on Reset and should be initialized before
clearing T0IF bit.
3: Includes ULPWU interrupt.
DS41232D-page 28
© 2007 Microchip Technology Inc.
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