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PIC12F629EP 参数 Datasheet PDF下载

PIC12F629EP图片预览
型号: PIC12F629EP
PDF下载: 下载PDF文件 查看货源
内容描述: 8引脚基于闪存的8位CMOS微控制器 [8-Pin FLASH-Based 8-Bit CMOS Microcontrollers]
分类和应用: 闪存微控制器
文件页数/大小: 132 页 / 4519 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12F629/675  
2.2.2.3  
INTCON Register  
Note: Interrupt flag bits are set when an interrupt  
condition occurs, regardless of the state of  
its corresponding enable bit or the global  
enable bit, GIE (INTCON<7>). User soft-  
ware should ensure the appropriate  
interrupt flag bits are clear prior to enabling  
an interrupt.  
The INTCON register is a readable and writable  
register, which contains the various enable and flag bits  
for TMR0 register overflow, GPIO port change and  
external GP2/INT pin interrupts.  
REGISTER 2-3:  
INTCON — INTERRUPT CONTROL REGISTER (ADDRESS: 0Bh OR 8Bh)  
R/W-0  
GIE  
R/W-0  
PEIE  
R/W-0  
T0IE  
R/W-0  
INTE  
R/W-0  
GPIE  
R/W-0  
T0IF  
R/W-0  
INTF  
R/W-0  
GPIF  
bit 7  
bit 0  
bit 7  
bit 6  
bit 5  
bit 4  
bit 3  
bit 2  
bit ±  
bit 0  
GIE: Global Interrupt Enable bit  
1= Enables all unmasked interrupts  
0= Disables all interrupts  
PEIE: Peripheral Interrupt Enable bit  
1= Enables all unmasked peripheral interrupts  
0= Disables all peripheral interrupts  
T0IE: TMR0 Overflow Interrupt Enable bit  
1= Enables the TMR0 interrupt  
0= Disables the TMR0 interrupt  
INTE: GP2/INT External Interrupt Enable bit  
1= Enables the GP2/INT external interrupt  
0= Disables the GP2/INT external interrupt  
(1)  
GPIE: Port Change Interrupt Enable bit  
1= Enables the GPIO port change interrupt  
0= Disables the GPIO port change interrupt  
(2)  
T0IF: TMR0 Overflow Interrupt Flag bit  
1= TMR0 register has overflowed (must be cleared in software)  
0= TMR0 register did not overflow  
INTF: GP2/INT External Interrupt Flag bit  
1= The GP2/INT external interrupt occurred (must be cleared in software)  
0= The GP2/INT external interrupt did not occur  
GPIF: Port Change Interrupt Flag bit  
1= When at least one of the GP5:GP0 pins changed state (must be cleared in software)  
0= None of the GP5:GP0 pins have changed state  
Note 1: IOC register must also be enabled to enable an interrupt-on-change.  
2: T0IF bit is set when TIMER0 rolls over. TIMER0 is unchanged on RESET and  
should be initialized before clearing T0IF bit.  
Legend:  
R = Readable bit  
W = Writable bit  
’±’ = Bit is set  
U = Unimplemented bit, read as ‘0’  
’0’ = Bit is cleared x = Bit is unknown  
- n = Value at POR  
2003 Microchip Technology Inc.  
DS41190C-page 13  
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