欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC12F629EP 参数 Datasheet PDF下载

PIC12F629EP图片预览
型号: PIC12F629EP
PDF下载: 下载PDF文件 查看货源
内容描述: 8引脚基于闪存的8位CMOS微控制器 [8-Pin FLASH-Based 8-Bit CMOS Microcontrollers]
分类和应用: 闪存微控制器
文件页数/大小: 132 页 / 4519 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC12F629EP的Datasheet PDF文件第8页浏览型号PIC12F629EP的Datasheet PDF文件第9页浏览型号PIC12F629EP的Datasheet PDF文件第10页浏览型号PIC12F629EP的Datasheet PDF文件第11页浏览型号PIC12F629EP的Datasheet PDF文件第13页浏览型号PIC12F629EP的Datasheet PDF文件第14页浏览型号PIC12F629EP的Datasheet PDF文件第15页浏览型号PIC12F629EP的Datasheet PDF文件第16页  
PIC12F629/675  
TABLE 2-1:  
Address  
SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)  
Value on  
POR, BOD  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Page  
Bank 1  
80h  
81h  
82h  
83h  
INDF(1)  
Addressing this Location uses Contents of FSR to Address Data Memory  
0000 0000 18,59  
1111 1111 12,28  
OPTION_REG  
PCL  
GPPU  
INTEDG  
T0CS  
T0SE  
PSA  
PS2  
PS1  
DC  
PS0  
C
Program Counter's (PC) Least Significant Byte  
0000 0000  
0001 1xxx  
17  
11  
IRP(2)  
Indirect Data Memory Address Pointer  
RP1(2)  
STATUS  
RP0  
TO  
PD  
Z
84h  
85h  
86h  
87h  
88h  
89h  
8Ah  
8Bh  
8Ch  
8Dh  
8Eh  
8Fh  
90h  
91h  
92h  
93h  
94h  
95h  
96h  
97h  
98h  
99h  
9Ah  
9Bh  
9Ch  
9Dh  
9Eh  
9Fh  
Legend:  
FSR  
xxxx xxxx  
18  
19  
17  
13  
14  
16  
16  
20  
21  
40  
47  
47  
48  
48  
42  
TRISIO  
TRISIO5  
TRISIO4  
TRISIO3  
TRISIO2  
TRISIO1  
TRISIO0 --11 1111  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
PCLATH  
INTCON  
PIE1  
T0IE  
Write Buffer for Upper 5 bits of Program Counter  
---0 0000  
GIE  
PEIE  
ADIE  
INTE  
GPIE  
CMIE  
T0IF  
INTF  
GPIF  
0000 0000  
00-- 0--0  
EEIE  
TMR1IE  
Unimplemented  
PCON  
POR  
BOD  
---- --0x  
Unimplemented  
CAL5  
OSCCAL  
CAL4  
CAL3  
CAL2  
CAL1  
CAL0  
1000 00--  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
WPU  
IOC  
WPU5  
IOC5  
WPU4  
IOC4  
WPU2  
IOC2  
WPU1  
IOC1  
WPU0  
IOC0  
--11 -111  
--00 0000  
IOC3  
Unimplemented  
Unimplemented  
VREN  
VRCON  
EEDATA  
EEADR  
EECON1  
EECON2(1)  
ADRESL(3)  
ANSEL(3)  
0-0- 0000  
0000 0000  
-000 0000  
---- x000  
---- ----  
xxxx xxxx  
VRR  
VR3  
VR2  
VR1  
VR0  
RD  
Data EEPROM Data Register  
Data EEPROM Address Register  
WRERR  
WREN  
WR  
EEPROM Control Register 2  
Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result  
ADCS2 ADCS1 ADCS0 ANS3 ANS2 ANS1  
ANS0  
-000 1111 44,59  
— = unimplemented locations read as ‘0’, u= unchanged, x= unknown, q= value depends on condition,  
shaded = unimplemented  
Note 1: This is not a physical register.  
2: These bits are reserved and should always be maintained as ‘0’.  
3: PIC12F675 only.  
DS41190C-page 10  
2003 Microchip Technology Inc.