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PIC12F629-I/P 参数 Datasheet PDF下载

PIC12F629-I/P图片预览
型号: PIC12F629-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 8引脚, 8位CMOS微控制器与A / D转换器和EEPROM数据存储器 [8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory]
分类和应用: 转换器存储微控制器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 116 页 / 649 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12CE67X  
TABLE 4-1:  
Address Name  
Bank 1  
PIC12CE67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.)  
Value on  
Power-on  
Reset  
Value on  
all other  
Resets(3)  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
80h(1)  
81h  
INDF  
OPTION  
PCL  
STATUS  
FSR  
TRIS  
Addressing this location uses contents of FSR to address data memory (not a physical register)  
0000 0000 0000 0000  
1111 1111 1111 1111  
0000 0000 0000 0000  
0001 1xxx 000q quuu  
xxxx xxxx uuuu uuuu  
0011 1111 0011 1111  
GPPU  
Program Counter's (PC) Least Significant Byte  
IRP(4) RP1(4)  
RP0 TO  
Indirect data memory address pointer  
INTEDG  
T0CS  
T0SE  
PSA  
PS2  
PS1  
PS0  
82h(1)  
83h(1)  
84h(1)  
85h  
PD  
Z
DC  
C
GPIO Data Direction Register  
86h  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
87h  
88h  
89h  
8Ah(1,2) PCLATH  
T0IE  
Write Buffer for the upper 5 bits of the PC  
---0 0000 ---0 0000  
0000 000x 0000 000u  
-0-- ---- -0-- ----  
8Bh(1)  
8Ch  
8Dh  
8Eh  
8Fh  
90h  
91h  
92h  
93h  
94h  
95h  
96h  
97h  
98h  
99h  
9Ah  
9Bh  
9Ch  
9Dh  
9Eh  
9Fh  
INTCON  
GIE  
PEIE  
ADIE  
INTE  
GPIE  
T0IF  
INTF  
GPIF  
PIE1  
Unimplemented  
PCON  
POR  
---- --0- ---- --u-  
1000 00-- uuuu uu--  
OSCCAL  
CAL5  
CAL4  
CAL3  
CAL2  
CAL1  
CAL0  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
Unimplemented  
ADCON1  
PCFG2  
PCFG1  
PCFG0  
---- -000 ---- -000  
Legend: x= unknown, u= unchanged, q= value depends on condition, - = unimplemented read as '0', r = reserved.  
Shaded locations are unimplemented, read as ‘0’.  
Note 1: These registers can be addressed from either bank.  
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose  
contents are transferred to the upper byte of the program counter.  
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.  
4: The IRP and RP1 bits are reserved on the PIC12CE67X, always maintain these bits clear.  
DS40181B-page 14  
Preliminary  
1998 Microchip Technology Inc.