PIC12CE67X
FIGURE 4-2:
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
INDF
(1)
TMR0
PCL
STATUS
FSR
GPIO
INDF
(1)
OPTION
PCL
STATUS
FSR
TRIS
PIC12CE67X REGISTER FILE
MAP
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
PCLATH
INTCON
PIR1
PCLATH
INTCON
PIE1
PCON
OSCCAL
ADRES
ADCON0
ADCON1
General
Purpose
Register
General
Purpose
Register
70h
7Fh
Bank 0
Mapped
in Bank 0
Bank 1
BFh
C0h
EFh
F0h
FFh
Unimplemented data memory locations, read
as '0'.
Note 1: Not a physical register.
DS40181B-page 12
Preliminary
©
1998 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
