PIC12F629/675
5.1
Timer1 Modes of Operation
5.2
Timer1 Interrupt
Timer± can operate in one of three modes:
The Timer± register pair (TMR±H:TMR±L) increments
to FFFFh and rolls over to 0000h. When Timer± rolls
over, the Timer± interrupt flag bit (PIR±<0>) is set. To
enable the interrupt on rollover, you must set these bits:
• ±6-bit timer with prescaler
• ±6-bit synchronous counter
• ±6-bit asynchronous counter
• Timer± interrupt Enable bit (PIE±<0>)
• PEIE bit (INTCON<6>)
In Timer mode, Timer± is incremented on every
instruction cycle. In Counter mode, Timer± is incre-
mented on the rising edge of the external clock input
T±CKI. In addition, the Counter mode clock can be
synchronized to the microcontroller system clock or
run asynchronously.
• GIE bit (INTCON<7>).
The interrupt is cleared by clearing the TMR±IF in the
Interrupt Service Routine.
Note: The TMR±H:TTMR±L register pair and the
TMR±IF bit should be cleared before
enabling interrupts.
In Counter and Timer modules, the counter/timer clock
can be gated by the T±G input.
If an external clock oscillator is needed (and the
microcontroller is using the INTOSC w/o CLKOUT),
Timer± can use the LP oscillator as a clock source.
5.3
Timer1 Prescaler
Timer± has four prescaler options allowing ±, 2, 4, or 8
divisions of the clock input. The T±CKPS bits
(T±CON<5:4>) control the prescale counter. The
prescale counter is not directly readable or writable;
however, the prescaler counter is cleared upon a write
to TMR±H or TMR±L.
Note: In Counter mode, a falling edge must be
registered by the counter prior to the first
incrementing rising edge.
FIGURE 5-2:
TIMER1 INCREMENTING EDGE
T1CKI = 1
when TMR1
Enabled
T1CKI = 0
when TMR1
Enabled
Note 1: Arrows indicate counter increments.
2: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the
clock.
2003 Microchip Technology Inc.
DS41190C-page 31
MICROCHIP [ MICROCHIP ]
