PIC12F629/675
EXAMPLE 4-1:
CHANGING PRESCALER
(TIMER0→WDT)
4.4
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this Data Sheet. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS2:PS0 bits (OPTION_REG<2:0>).
bcf
STATUS,RP0 ;Bank 0
clrwdt
clrf
;Clear WDT
TMR0
;Clear TMR0 and
; prescaler
bsf
STATUS,RP0 ;Bank 1
movlw
movwf
clrwdt
b’00101111’ ;Required if desired
OPTION_REG ; PS2:PS0 is
; 000 or 001
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
;
movlw
movwf
bcf
b’00101xxx’ ;Set postscaler to
OPTION_REG ; desired WDT rate
STATUS,RP0 ;Bank 0
4.4.1
SWITCHING PRESCALER
ASSIGNMENT
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 4-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
EXAMPLE 4-2:
CHANGING PRESCALER
(WDT→TIMER0)
RESET,
the
following
instruction
sequence
(Example 4-±) must be executed when changing the
prescaler assignment from Timer0 to WDT.
clrwdt
;Clear WDT and
; postscaler
bsf
STATUS,RP0 ;Bank 1
movlw
b’xxxx0xxx’ ;Select TMR0,
; prescale, and
; clock source
;
movwf
bcf
OPTION_REG
STATUS,RP0 ;Bank 0
TABLE 4-1:
REGISTERS ASSOCIATED WITH TIMER0
Value on
all other
RESETS
Value on
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
POR, BOD
01h
TMR0
Timer0 Module Register
GIE PEIE T0IE
xxxx xxxx uuuu uuuu
0000 0000 0000 000u
0Bh/8Bh INTCON
INTE
T0SE
GPIE
PSA
T0IF
PS2
INTF
PS1
GPIF
PS0
81h
OPTION_REG
TRISIO
GPPU INTEDG T0CS
1111 1111 1111 1111
85h
—
—
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
Legend:
— = Unimplemented locations, read as ‘0’, u= unchanged, x= unknown.
Shaded cells are not used by the Timer0 module.
2003 Microchip Technology Inc.
DS41190C-page 29
MICROCHIP [ MICROCHIP ]
