PIC12F629/675
FIGURE 12-10:
PIC12F675 A/D CONVERSION TIMING (NORMAL MODE)
BSF ADCON0, GO
134
Q4
1 TCY
(TOSC/2)(1)
131
130
A/D CLK
9
8
7
6
3
2
1
0
A/D DATA
ADRES
NEW_DATA
1 TCY
OLD_DATA
ADIF
GO
DONE
SAMPLING STOPPED
132
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEPinstruction to be executed.
TABLE 12-9: PIC12F675 A/D CONVERSION REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
Conditions
±30
TAD
A/D Clock Period
±.6
—
—
—
—
µs TOSC based, VREF ≥ 3.0V
µs TOSC based, VREF full range
3.0*
±30
TAD
A/D Internal RC
Oscillator Period
ADCS<±:0> = 11(RC mode)
µs At VDD = 2.5V
3.0*
2.0*
—
6.0
4.0
±±
9.0*
6.0*
—
µs At VDD = 5.0V
±3±
±32
TCNV Conversion Time
(not including
Acquisition Time)
TAD Set GO bit to new data in A/D result
register
(1)
TACQ Acquisition Time
(Note 2)
±±.5
—
—
—
µs
5*
µs The minimum time is the amplifier
settling time. This may be used if the
“new” input voltage has not changed
by more than ± LSb (i.e., 4.± mV @
4.096V) from the last sampled
voltage (as stored on CHOLD).
±34
TGO
Q4 to A/D Clock
Start
—
TOSC/2
—
—
If the A/D clock source is selected as
RC, a time of TCY is added before
the A/D clock starts. This allows the
SLEEPinstruction to be executed.
* These parameters are characterized but not tested.
† Data in ‘Typ’ column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 7.± for minimum conditions.
DS41190C-page 102
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
