PIC12F629/675
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
0 ≤ k ≤ 2047
Syntax:
[ label ] CLRWDT
Operands:
Operation:
Operands:
Operation:
None
(PC)+ ±→ TOS,
k → PC<±0:0>,
(PCLATH<4:3>) → PC<±2:±±>
00h → WDT
0 → WDT prescaler,
± → TO
± → PD
Status Affected: None
Status Affected: TO, PD
Description:
Call Subroutine. First, return
address (PC+±) is pushed onto
the stack. The eleven-bit immedi-
ate address is loaded into PC bits
<±0:0>. The upper bits of the PC
are loaded from PCLATH. CALLis
a two-cycle instruction.
Description:
CLRWDTinstruction resets the
Watchdog Timer. It also resets
the prescaler of the WDT.
STATUS bits TO and PD are set.
CLRF
Clear f
COMF
Complement f
Syntax:
[label] CLRF
0 ≤ f ≤ ±27
f
Syntax:
[ label ] COMF f,d
Operands:
Operation:
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
00h → (f)
± → Z
Operation:
(f) → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
The contents of register 'f' are
cleared and the Z bit is set.
The contents of register 'f' are
complemented. If 'd' is 0, the
result is stored in W. If 'd' is ±, the
result is stored back in register 'f'.
CLRW
Clear W
DECF
Decrement f
Syntax:
[ label ] CLRW
Syntax:
[label] DECF f,d
Operands:
Operation:
None
Operands:
0 ≤ f ≤ ±27
d ∈ [0,±]
00h → (W)
± → Z
Operation:
(f) - ± → (destination)
Status Affected:
Description:
Z
Status Affected:
Description:
Z
W register is cleared. Zero bit (Z)
is set.
Decrement register 'f'. If 'd' is 0,
the result is stored in the W
register. If 'd' is ±, the result is
stored back in register 'f'.
DS41190C-page 72
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
