PIC12F629/675
TABLE 10-2: PIC12F629/675 INSTRUCTION SET
14-Bit Opcode
Mnemonic,
Description
Operands
Status
Cycles
Notes
Affected
MSb
LSb
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
f, d
f, d
f
Add W and f
1
1
00 0111 dfff ffff C,DC,Z
1,2
1,2
2
AND W with f
00 0101 dfff ffff
00 0001 lfff ffff
00 0001 0xxx xxxx
00 1001 dfff ffff
00 0011 dfff ffff
00 1011 dfff ffff
00 1010 dfff ffff
00 1111 dfff ffff
00 0100 dfff ffff
00 1000 dfff ffff
00 0000 lfff ffff
00 0000 0xx0 0000
00 1101 dfff ffff
00 1100 dfff ffff
Z
Z
Z
Z
Z
Clear f
1
CLRW
COMF
DECF
-
Clear W
1
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
Complement f
1
1,2
1,2
Decrement f
1
DECFSZ
INCF
Decrement f, Skip if 0
Increment f
1(2)
1
1,2,3
1,2
Z
INCFSZ
IORWF
MOVF
MOVWF
NOP
Increment f, Skip if 0
Inclusive OR W with f
Move f
1(2)
1
1,2,3
1,2
Z
Z
1
1,2
Move W to f
1
-
No Operation
1
RLF
f, d
f, d
f, d
f, d
f, d
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
C
C
1,2
1,2
1,2
1,2
1,2
RRF
1
SUBWF
SWAPF
XORWF
1
00 0010 dfff ffff C,DC,Z
00 1110 dfff ffff
1
1
00 0110 dfff ffff
Z
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
f, b
f, b
f, b
f, b
Bit Clear f
1
01 00bb bfff ffff
1,2
1,2
3
BSF
Bit Set f
1
01 01bb bfff ffff
01 10bb bfff ffff
01 11bb bfff ffff
BTFSC
BTFSS
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1 (2)
1 (2)
3
LITERAL AND CONTROL OPERATIONS
ADDLW
ANDLW
CALL
k
k
k
-
Add literal and W
1
1
2
1
2
1
1
2
2
2
1
1
1
11 111x kkkk kkkk C,DC,Z
AND literal with W
11 1001 kkkk kkkk
10 0kkk kkkk kkkk
00 0000 0110 0100
10 1kkk kkkk kkkk
11 1000 kkkk kkkk
11 00xx kkkk kkkk
00 0000 0000 1001
11 01xx kkkk kkkk
00 0000 0000 1000
00 0000 0110 0011
Z
TO,PD
Z
Call subroutine
CLRWDT
GOTO
Clear Watchdog Timer
Go to address
k
k
k
-
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
k
-
-
TO,PD
k
k
11 110x kkkk kkkk C,DC,Z
11 1010 kkkk kkkk
Z
Note 1: When an I/O register is modified as a function of itself (e.g., MOVF GPIO, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 module.
3: If Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note: Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).
DS41190C-page 70
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
