PIC12F629/675
The output of the sample and hold is connected to the
input of the converter. The converter generates a
binary result via successive approximation and stores
the result in a ±0-bit register. The voltage reference
used in the conversion is software selectable to either
VDD or a voltage applied by the VREF pin. Figure 7-±
shows the block diagram of the A/D on the PIC±2F675.
7.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
(PIC12F675 ONLY)
The analog-to-digital converter (A/D) allows conversion
of an analog input signal to a ±0-bit binary representa-
tion of that signal. The PIC±2F675 has four analog
inputs, multiplexed into one sample and hold circuit.
FIGURE 7-1:
A/D BLOCK DIAGRAM
VDD
VCFG = 0
VCFG = 1
VREF
GP0/AN0
GP1/AN1/VREF
GP2/AN2
ADC
10
GO/DONE
GP4/AN3
ADFM
CHS1:CHS0
10
ADON
ADRESH ADRESL
VSS
controls the voltage reference selection. If VCFG is set,
then the voltage on the VREF pin is the reference;
otherwise, VDD is the reference.
7.1
A/D Configuration and Operation
There are two registers available to control the
functionality of the A/D module:
7.1.4
CONVERSION CLOCK
±. ADCON0 (Register 7-±)
2. ANSEL (Register 7-2)
The A/D conversion cycle requires ±± TAD. The source
of the conversion clock is software selectable via the
ADCS bits (ANSEL<6:4>). There are seven possible
clock options:
7.1.1
ANALOG PORT PINS
The ANS3:ANS0 bits (ANSEL<3:0>) and the TRISIO
bits control the operation of the A/D port pins. Set the
corresponding TRISIO bits to set the pin output driver
to its high impedance state. Likewise, set the
corresponding ANS bit to disable the digital input
buffer.
• FOSC/2
• FOSC/4
• FOSC/8
• FOSC/±6
• FOSC/32
Note: Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
• FOSC/64
• FRC (dedicated internal RC oscillator)
For correct conversion, the A/D conversion clock
(±/TAD) must be selected to ensure a minimum TAD of
±.6 µs. Table 7-± shows a few TAD calculations for
selected frequencies.
7.1.2
CHANNEL SELECTION
There are four analog channels on the PIC±2F675,
AN0 through AN3. The CHS±:CHS0 bits
(ADCON0<3:2>) control which channel is connected to
the sample and hold circuit.
7.1.3
VOLTAGE REFERENCE
There are two options for the voltage reference to the
A/D converter: either VDD is used, or an analog voltage
applied to VREF is used. The VCFG bit (ADCON0<6>)
2003 Microchip Technology Inc.
DS41190C-page 41
MICROCHIP [ MICROCHIP ]
