PIC12F629/675
The Timer± Control register (T±CON), shown in
Register 5-±, is used to enable/disable Timer± and
select the various features of the Timer± module.
5.0
TIMER1 MODULE WITH GATE
CONTROL
The PIC±2F629/675 devices have a ±6-bit timer.
Figure 5-± shows the basic block diagram of the Timer±
module. Timer± has the following features:
Note: Additional information on timer modules is
available in the PICmicroTM Mid-Range
Reference Manual, (DS33023).
• ±6-bit timer/counter (TMR±H:TMR±L)
• Readable and writable
• Internal or external clock selection
• Synchronous or asynchronous operation
• Interrupt on overflow from FFFFh to 0000h
• Wake-up upon overflow (Asynchronous mode)
• Optional external enable input (T±G)
• Optional LP oscillator
FIGURE 5-1:
TIMER1 BLOCK DIAGRAM
TMR1ON
TMR1GE
T1G
TMR1ON
TMR1GE
Set Flag bit
TMR1IF on
Overflow
TMR1
Synchronized
0
Clock Input
TMR1L
TMR1H
1
LP Oscillator
T1SYNC
OSC1
OSC2
1
0
Synchronize
Detect
Prescaler
1, 2, 4, 8
FOSC/4
Internal
Clock
2
SLEEP Input
T1CKPS<1:0>
INTOSC
w/o CLKOUT
TMR1CS
T1OSCEN
LP
DS41190C-page 30
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
