PIC12F629/675
a small RC delay of 20 ns) and low for at least 2TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
4.3
Using Timer0 with an External
Clock
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2TOSC (and
Note: The ANSEL (9Fh) and CMCON (±9h)
registers must be initialized to configure an
analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
The ANSEL register is defined for the
PIC±2F675.
REGISTER 4-1:
OPTION_REG — OPTION REGISTER (ADDRESS: 81h)
R/W-±
GPPU
R/W-±
R/W-±
T0CS
R/W-±
T0SE
R/W-±
PSA
R/W-±
PS2
R/W-±
PS±
R/W-±
PS0
INTEDG
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
GPPU: GPIO Pull-up Enable bit
1= GPIO pull-ups are disabled
0= GPIO pull-ups are enabled by individual port latch values
INTEDG: Interrupt Edge Select bit
1= Interrupt on rising edge of GP2/INT pin
0= Interrupt on falling edge of GP2/INT pin
T0CS: TMR0 Clock Source Select bit
1= Transition on GP2/T0CKI pin
0= Internal instruction cycle clock (CLKOUT)
T0SE: TMR0 Source Edge Select bit
1= Increment on high-to-low transition on GP2/T0CKI pin
0= Increment on low-to-high transition on GP2/T0CKI pin
PSA: Prescaler Assignment bit
1= Prescaler is assigned to the WDT
0= Prescaler is assigned to the TIMER0 module
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
± : 2
± : 4
± : 8
± : ±6
± : 32
± : 64
± : ±28
± : 256
± : ±
± : 2
± : 4
± : 8
± : ±6
± : 32
± : 64
± : ±28
Legend:
R = Readable bit
W = Writable bit
’±’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared x = Bit is unknown
- n = Value at POR
DS41190C-page 28
2003 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
