PIC12F629/675
3.3.5
GP4/AN3/T1G/OSC2/CLKOUT
3.3.6
GP5/T1CKI/OSC1/CLKIN
Figure 3-4 shows the diagram for this pin. The GP4 pin
is configurable to function as one of the following:
Figure 3-5 shows the diagram for this pin. The GP5 pin
is configurable to function as one of the following:
• a general purpose I/O
• a general purpose I/O
• a TMR1 clock input
• a crystal/resonator connection
• a clock input
• an analog input for the A/D (PIC12F675 only)
• a TMR1 gate input
• a crystal/resonator connection
• a clock output
FIGURE 3-5:
BLOCK DIAGRAM OF GP5
FIGURE 3-4:
BLOCK DIAGRAM OF GP4
INTOSC
Mode
Analog
TMR1LPEN(1)
VDD
Input Mode
CLK
Data Bus
D
Modes(1)
VDD
Q
Q
Data Bus
D
Q
Q
WR
CK
Weak
WR
WPU
CK
WPU
Weak
GPPU
RD
GPPU
RD
WPU
WPU
Oscillator
Circuit
Oscillator
Circuit
OSC1
OSC2
VDD
VDD
D
Q
Q
CLKOUT
Enable
WR
PORT
CK
FOSC/4
1
0
D
Q
Q
I/O pin
I/O pin
WR
CK
D
Q
Q
PORT
CLKOUT
Enable
WR
TRISIO
CK
VSS
VSS
D
Q
Q
INTOSC
Mode
INTOSC/
RC/EC(2)
RD
TRISIO
WR
TRISIO
CK
CLKOUT
Enable
(2)
RD
PORT
RD
TRISIO
Analog
Input Mode
D
Q
Q
RD
PORT
Q
Q
D
CK
WR
IOC
D
Q
Q
EN
Q
D
D
RD
IOC
CK
WR
IOC
EN
D
RD
IOC
EN
Q
Interrupt-on-Change
EN
Interrupt-on-Change
RD PORT
RD PORT
To TMR1 or CLKGEN
To TMR1 T1G
To A/D Converter
Note 1: Timer1 LP Oscillator enabled
Note 1: CLK modes are XT, HS, LP, LPTMR1 and CLKOUT
Enable.
2: When using Timer1 with LP oscillator, the Schmitt
Trigger is by-passed.
2: With CLKOUT option.
DS41190G-page 26
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
