PIC12F629/675
3.3.3
GP2/AN2/T0CKI/INT/COUT
3.3.4
GP3/MCLR/VPP
Figure 3-2 shows the diagram for this pin. The GP2 pin
is configurable to function as one of the following:
Figure 3-3 shows the diagram for this pin. The GP3 pin
is configurable to function as one of the following:
• a general purpose I/O
• a general purpose input
• as Master Clear Reset
• an analog input for the A/D (PIC12F675 only)
• the clock input for TMR0
FIGURE 3-3:
BLOCK DIAGRAM OF GP3
• an external edge triggered interrupt
• a digital output from the comparator
Data Bus
MCLRE
I/O pin
Reset
FIGURE 3-2:
BLOCK DIAGRAM OF GP2
RD
TRISIO
VSS
Analog
Input Mode
Data Bus
D
MCLRE
VSS
Q
Q
VDD
RD
PORT
WR
CK
Weak
WPU
D
Q
Q
Q
Q
D
CK
WR
IOC
GPPU
Analog
RD
WPU
EN
COUT
Input
RD
IOC
Enable
Mode
D
VDD
D
Q
Q
EN
WR
PORT
CK
Interrupt-on-Change
COUT
1
0
RD PORT
I/O pin
D
Q
Q
WR
TRISIO
CK
VSS
Analog
Input Mode
RD
TRISIO
RD
PORT
D
Q
Q
Q
D
D
CK
WR
IOC
EN
RD
IOC
Q
EN
Interrupt-on-Change
RD PORT
To TMR0
To INT
To A/D Converter
2010 Microchip Technology Inc.
DS41190G-page 25
MICROCHIP [ MICROCHIP ]
