PIC12F629/675
REGISTER 6-2:
R/W-0
VRCON: VOLTAGE REFERENCE CONTROL REGISTER (ADDRESS: 99h)
U-0
—
R/W-0
VRR
R/W-0
—
R/W-0
VR3
R/W-0
VR2
R/W-0
VR1
R/W-0
VR0
VREN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
VREN: CVREF Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down, no IDD drain
bit 6
bit 5
Unimplemented: Read as ‘0’
VRR: CVREF Range Selection bit
1= Low range
0= High range
bit 4
Unimplemented: Read as ‘0’
bit 3-0
VR3:VR0: CVREF value selection 0 VR [3:0] 15
When VRR = 1: CVREF = (VR3:VR0 / 24) * VDD
When VRR = 0: CVREF = VDD/4 + (VR3:VR0 / 32) * VDD
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
6.9
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of the comparator.
Software will need to maintain information about the
status of the output bits, as read from CMCON<6>, to
determine the actual change that has occurred. The
CMIF bit, PIR1<3>, is the comparator interrupt flag.
This bit must be reset in software by clearing it to ‘0’.
Since it is also possible to write a ‘1’ to this register, a
simulated interrupt may be initiated.
a) Any read or write of CMCON. This will end the
mismatch condition.
b) Clear flag bit CMIF.
A mismatch condition will continue to set flag bit CMIF.
Reading CMCON will end the mismatch condition, and
allow flag bit CMIF to be cleared.
Note: If a change in the CMCON register (COUT)
should occur when a read operation is
being executed (start of the Q2 cycle), then
the CMIF (PIR1<3>) interrupt flag may not
get set.
The CMIE bit (PIE1<3>) and the PEIE bit (INT-
CON<6>) must be set to enable the interrupt. In addi-
tion, the GIE bit must also be set. If any of these bits are
cleared, the interrupt is not enabled, though the CMIF
bit will still be set if an interrupt condition occurs.
TABLE 6-2:
REGISTERS ASSOCIATED WITH COMPARATOR MODULE
Value on
Value on
POR, BOD
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
all other
Resets
0Bh/8Bh
0Ch
INTCON
PIR1
GIE
EEIF
—
PEIE
ADIF
COUT
ADIE
—
T0IE
—
INTE
—
GPIE
CMIF
CIS
T0IF
—
INTF
—
GPIF
0000 0000 0000 000u
TMR1IF 00-- 0--0 00-- 0--0
CM0
TMR1IE 00-- 0--0 00-- 0--0
19h
CMCON
PIE1
—
CINV
—
CM2
—
CM1
—
-0-0 0000 -0-0 0000
8Ch
EEIE
—
—
CMIE
85h
TRISIO
VRCON
TRISIO5 TRISIO4 TRISIO3 TRISIO2 TRISIO1 TRISIO0 --11 1111 --11 1111
VRR VR3 VR2 VR1 VR0 0-0- 0000 0-0- 0000
99h
VREN
—
—
Legend:
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the comparator module.
DS41190G-page 42
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP ]
