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PIC12F675-I/SNG 参数 Datasheet PDF下载

PIC12F675-I/SNG图片预览
型号: PIC12F675-I/SNG
PDF下载: 下载PDF文件 查看货源
内容描述: [暂无描述]
分类和应用: 闪存微控制器
文件页数/大小: 136 页 / 1422 K
品牌: MICROCHIP [ MICROCHIP ]
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PIC12F629/675  
Counter mode is selected by setting the T0CS bit  
(OPTION_REG<5>). In this mode, the Timer0 module  
will increment either on every rising or falling edge of  
pin GP2/T0CKI. The incrementing edge is determined  
4.0  
TIMER0 MODULE  
The Timer0 module timer/counter has the following  
features:  
by  
the  
source  
edge  
(T0SE)  
control  
bit  
• 8-bit timer/counter  
(OPTION_REG<4>). Clearing the T0SE bit selects the  
rising edge.  
• Readable and writable  
• 8-bit software programmable prescaler  
• Internal or external clock select  
• Interrupt on overflow from FFh to 00h  
• Edge select for external clock  
Note: Counter mode has specific external clock  
requirements. Additional information on  
these requirements is available in the PIC®  
Mid-Range  
(DS33023).  
Reference  
Manual,  
Figure 4-1 is a block diagram of the Timer0 module and  
the prescaler shared with the WDT.  
4.2  
Timer0 Interrupt  
Note: Additional information on the Timer0  
module is available in the PIC® Mid-Range  
Reference Manual, (DS33023).  
A Timer0 interrupt is generated when the TMR0  
register timer/counter overflows from FFh to 00h. This  
overflow sets the T0IF bit. The interrupt can be masked  
by clearing the T0IE bit (INTCON<5>). The T0IF bit  
(INTCON<2>) must be cleared in software by the  
Timer0 module Interrupt Service Routine before re-  
enabling this interrupt. The Timer0 interrupt cannot  
wake the processor from Sleep since the timer is shut-  
off during Sleep.  
4.1  
Timer0 Operation  
Timer mode is selected by clearing the T0CS bit  
(OPTION_REG<5>). In Timer mode, the Timer0  
module will increment every instruction cycle (without  
prescaler). If TMR0 is written, the increment is inhibited  
for the following two instruction cycles. The user can  
work around this by writing an adjusted value to the  
TMR0 register.  
FIGURE 4-1:  
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER  
CLKOUT  
(= FOSC/4)  
Data Bus  
0
1
8
1
SYNC 2  
Cycles  
TMR0  
T0CKI  
pin  
0
0
1
Set Flag bit T0IF  
on Overflow  
T0CS  
T0SE  
8-bit  
Prescaler  
PSA  
8
PSA  
1
0
PS0 - PS2  
WDT  
Time-out  
Watchdog  
Timer  
PSA  
WDTE  
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.  
2010 Microchip Technology Inc.  
DS41190G-page 29