PIC12F629/675
TABLE 2-1:
Address
Bank 1
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
WPU
IOC
—
—
VRCON
EEDATA
EEADR
EECON1
EECON2
ANSEL
(1)
SPECIAL FUNCTION REGISTERS SUMMARY (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
Page
INDF
(1)
OPTION_REG
PCL
STATUS
FSR
TRISIO
—
—
—
—
PCLATH
INTCON
PIE1
—
PCON
—
OSCCAL
—
—
—
—
Addressing this Location uses Contents of FSR to Address Data Memory
GPPU
IRP
(2)
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
GIE
EEIE
—
Unimplemented
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
—
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
—
Unimplemented
Unimplemented
VREN
—
—
—
—
—
WPU5
IOC5
WPU4
IOC4
—
IOC3
WPU2
IOC2
WPU1
IOC1
WPU0
IOC0
—
PEIE
ADIE
—
—
T0IE
—
—
Write Buffer for Upper 5 bits of Program Counter
INTE
—
—
GPIE
CMIE
—
T0IF
—
—
INTF
—
POR
GPIF
TMR1IE
BOD
INTEDG
RP1
(2)
—
T0CS
RP0
T0SE
TO
PSA
PD
PS2
Z
PS1
DC
PS0
C
Program Counter’s (PC) Least Significant Byte
0000 0000
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
—
—
—
—
—
—
—
—
—
—
—
—
Indirect Data Memory Address Pointer
TRISIO5
TRISIO4
TRISIO3
TRISIO2
TRISIO1
TRISIO0
--11 1111
—
—
—
—
---0 0000
0000 0000
00-- 0--0
—
---- --0x
—
1000 00--
—
—
—
—
--11 -111
--00 0000
—
—
Unimplemented
VRR
—
VR3
VR2
VR1
VR0
0-0- 0000
0000 0000
-000 0000
Data EEPROM Data Register
Data EEPROM Address Register
—
—
—
WRERR
WREN
WR
RD
---- x000
---- ----
xxxx xxxx
EEPROM Control Register 2
Least Significant 2 bits of the Left Shifted A/D Result of 8 bits or the Right Shifted Result
—
ADCS2
ADCS1
ADCS0
ANS3
ANS2
ANS1
ANS0
ADRESL
(3)
(3)
-000 1111
Legend:
— = unimplemented locations read as ‘
0
’,
u
= unchanged,
x
= unknown,
q
= value depends on condition,
shaded = unimplemented
Note 1:
This is not a physical register.
2:
These bits are reserved and should always be maintained as ‘
0
’.
3:
PIC12F675 only.
DS41190G-page 12
2010 Microchip Technology Inc.
MICROCHIP [ MICROCHIP TECHNOLOGY ]
