PIC12F629/675
TABLE 2-1:
Address
Bank 0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
INDF
(1)
TMR0
PCL
STATUS
FSR
GPIO
—
—
—
—
PCLATH
INTCON
PIR1
—
TMR1L
TMR1H
T1CON
—
—
—
—
—
—
—
—
CMCON
—
—
—
—
ADRESH
(3)
ADCON0
(3)
Addressing this Location uses Contents of FSR to Address Data Memory
Timer0 Module’s Register
Program Counter’s (PC) Least Significant Byte
IRP
(2)
—
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
GIE
EEIF
—
PEIE
ADIF
—
T0IE
—
Write Buffer for Upper 5 bits of Program Counter
INTE
—
GPIE
CMIF
T0IF
—
INTF
—
GPIF
TMR1IF
RP1
(2)
—
RP0
GPIO5
TO
GPIO4
PD
GPIO3
Z
GPIO2
DC
GPIO1
C
GPIO0
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--xx xxxx
—
—
—
—
---0 0000
0000 0000
00-- 0--0
—
xxxx xxxx
xxxx xxxx
TMR1CS
TMR1ON
-000 0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTERS SUMMARY
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOD
Page
Indirect Data Memory Address Pointer
Unimplemented
Holding Register for the Least Significant Byte of the 16-bit Timer1
Holding Register for the Most Significant Byte of the 16-bit Timer1
—
TMR1GE
T1CKPS1
T1CKPS0
T1OSCEN
T1SYNC
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
—
COUT
CINV
CIS
CM2
CM1
CM0
-0-0 0000
—
—
—
—
xxxx xxxx
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Most Significant 8 bits of the Left Shifted A/D Result or 2 bits of the Right Shifted Result
ADFM
VCFG
—
—
CHS1
CHS0
GO/DONE
ADON
00-- 0000
Legend:
— = unimplemented locations read as ‘
0
’,
u
= unchanged,
x
= unknown,
q
= value depends on condition,
shaded = unimplemented
Note 1:
This is not a physical register.
2:
These bits are reserved and should always be maintained as ‘
0
’.
3:
PIC12F675 only.
2010 Microchip Technology Inc.
DS41190G-page 11
MICROCHIP [ MICROCHIP TECHNOLOGY ]
