欢迎访问ic37.com |
会员登录 免费注册
发布采购

PIC10F200-I/P 参数 Datasheet PDF下载

PIC10F200-I/P图片预览
型号: PIC10F200-I/P
PDF下载: 下载PDF文件 查看货源
内容描述: 6引脚8位闪存微控制器 [6-Pin, 8-Bit Flash Microcontrollers]
分类和应用: 闪存微控制器和处理器外围集成电路光电二极管PC时钟
文件页数/大小: 96 页 / 1447 K
品牌: MICROCHIP [ MICROCHIP ]
 浏览型号PIC10F200-I/P的Datasheet PDF文件第47页浏览型号PIC10F200-I/P的Datasheet PDF文件第48页浏览型号PIC10F200-I/P的Datasheet PDF文件第49页浏览型号PIC10F200-I/P的Datasheet PDF文件第50页浏览型号PIC10F200-I/P的Datasheet PDF文件第52页浏览型号PIC10F200-I/P的Datasheet PDF文件第53页浏览型号PIC10F200-I/P的Datasheet PDF文件第54页浏览型号PIC10F200-I/P的Datasheet PDF文件第55页  
PIC10F200/202/204/206  
FIGURE 9-9:  
BROWN-OUT  
9.9.2  
WAKE-UP FROM SLEEP  
PROTECTION CIRCUIT 3  
The device can wake-up from Sleep through one of  
the following events:  
VDD  
1. An external Reset input on GP3/MCLR/VPP pin,  
when configured as MCLR.  
MCP809  
VDD  
Bypass  
Capacitor  
VSS  
VDD  
2. A Watchdog Timer time-out Reset (if WDT was  
enabled).  
RST  
MCLR  
3. A change on input pin GP0, GP1 or GP3 when  
wake-up on change is enabled.  
PIC10F20X  
4. A comparator output change has occurred when  
wake-up on comparator change is enabled.  
Note:  
This brown-out protection circuit employs  
Microchip Technology’s MCP809 micro-  
controller supervisor. There are 7 different  
trip point selections to accommodate 5V to  
3V systems.  
These events cause a device Reset. The TO, PD  
GPWUF and CWUF bits can be used to determine the  
cause of device Reset. The TO bit is cleared if a WDT  
time-out occurred (and caused wake-up). The PD bit,  
which is set on power-up, is cleared when SLEEP is  
invoked. The GPWUF bit indicates a change in state  
while in Sleep at pins GP0, GP1 or GP3 (since the last  
file or bit operation on GP port). The CWUF bit  
indicates a change in the state while in Sleep of the  
comparator output.  
9.9  
Power-Down Mode (Sleep)  
A device may be powered down (Sleep) and later  
powered up (wake-up from Sleep).  
9.9.1  
SLEEP  
Note:  
Caution: Right before entering Sleep,  
read the input pins. When in Sleep, wake-  
up occurs when the values at the pins  
change from the state they were in at the  
last reading. If a wake-up on change  
occurs and the pins are not read before re-  
entering Sleep, a wake-up will occur  
immediately even if no pins change while  
in Sleep mode.  
The Power-Down mode is entered by executing a  
SLEEPinstruction.  
If enabled, the Watchdog Timer will be cleared but  
keeps running, the TO bit (STATUS<4>) is set, the PD  
bit (STATUS<3>) is cleared and the oscillator driver is  
turned off. The I/O ports maintain the status they had  
before the SLEEP instruction was executed (driving  
high, driving low or high-impedance).  
Note:  
A Reset generated by a WDT time-out  
does not drive the MCLR pin low.  
Note:  
The WDT is cleared when the device  
wakes from Sleep, regardless of the wake-  
up source.  
For lowest current consumption while powered down,  
the T0CKI input should be at VDD or VSS and the GP3/  
MCLR/VPP pin must be at a logic high level if MCLR is  
enabled.  
© 2007 Microchip Technology Inc.  
DS41239D-page 49  
 复制成功!